Accelerator Functional Unit Developer Guide: Intel FPGA Programmable Acceleration Card N3000 Variants

ID 683190
Date 7/15/2022
Document Table of Contents Directory Structure

The supplied FPGA files are a combination of clear text and encrypted files.

The directory structure of the supplied source files is shown below:

Directory Structure of the Factory_Image sub directory:

  • /hw/afu – this is where the AFU factory image example is located
    • /hw - Sub directory with clear text RTL, afu.qsf and afu.sdc
    • /sw - Sub directory with example software code
  • /hw/pac – this is where Ethernet MAC, external memory interface, and encrypted FIM is included
  • /prj/pac_baseline Intel® Quartus® Prime project files
  • /prj/pac_baseline/build – programming files and build reports after compilation completes
  • At the top of the directory tree is the Makefile used in compiling the project.
  • The hello_afu sub directory contains a simple example AFU illustrating design points. The Initial_Shell_AFU contains a starting directory structure for your new AFU design.