Accelerator Functional Unit Developer Guide: Intel FPGA Programmable Acceleration Card N3000 Variants

ID 683190
Date 7/15/2022
Document Table of Contents Ethernet Interface

The N3000 has Ethernet MAC IP cores to provide Ethernet receive packet delineation and transmit packet origination. The Ethernet MACs are instantiated in both the network interface and the N3000 Intel® Ethernet Controller XL710-BM2 NIC interface, as shown below:
Figure 11. Instantiated Ethernet MACs
The nfv_eth_wrapper module is configurable by Verilog parameters for the type of Ethernet interface (10, 25 or 40 G), number of interfaces and aggregated or disaggregated style of the AFU interface. The setting of these Verilog parameters is performed by the Makefile option settings described in the Build with make section. The nfv_eth_wrapper module includes the following:
  • Ethernet MAC
  • PLL
  • Multiplex/De-Multiplex blocks

The AFU Ethernet interface has three options with the following properties:


  1. One Avalon® streaming interface bus aggregating all traffic from each Ethernet interface
  2. Common clock
  3. Each Ethernet channel is identified by Avalon® streaming interface channel identifier
  4. Full Ethernet MAC statistics provided
The aggregated option allows your AFU to have a common packet processing pipeline. The aggregated option uses more FPGA resources and introduces delay from a packet buffer.
Figure 12. 8x10G Multiplexor
Figure 13. 8x10 De-Multiplexor


  1. Each Ethernet MAC has an Avalon® streaming interface bus provided as an array of Avalon® streaming interface. Each channel is identified by array index.
  2. Received packets with errors (CRC, length errors) are dropped from MAC.
  3. Egress FIFO saturation based flow control is provided to AFU.
  4. One common clock is used by AFU logic.
The disaggregated configuration reduces FPGA resources removing the multiplex/de-multiplex blocks.
Figure 14. MAC RX Packet MUX
Figure 15. MAC TX DEMUX

Lightweight Mode

  1. Disaggregated Avalon® streaming interface interfaces from each MAC.
  2. MUX function passes received traffic directly to the AFU.
  3. The AFU must control the data stream by removing frames with errors and controlling the flow.
  4. Each MAC interface has a separate clock.
  5. No Ethernet statistics provided in Ethernet MACs.
Note: The Lightweight mode is not supported for 10G applications.
Figure 16. MAC RX Packet MUX
Figure 17. MAC TX DEMUX