Accelerator Functional Unit Developer Guide: Intel FPGA Programmable Acceleration Card N3000 Variants

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ID 683190
Date 7/15/2022
Public
Document Table of Contents
Document Table of Contents x
1. About This Document 2. Introduction 3. High Level Description 4. Creating an N3000 FPGA Design 5. Capturing Signals in AFU with Signal Tap 6. Document Revision History for the Accelerator Functional Unit Developer Guide: Intel FPGA Programmable Acceleration Card N3000 Variants
1. About This Document x
1.1. Acronym List
2. Introduction x
2.1. Base Knowledge and Skills Prerequisites
2.1. Base Knowledge and Skills Prerequisites x
2.1.1. Considerations
3. High Level Description x
3.1. Steps for Creating Your AFU 3.2. N3000 Block Diagram 3.3. Factory Image Description
3.2. N3000 Block Diagram x
3.2.1. In-Line Data Path 3.2.2. Supported Ethernet Network Configurations 3.2.3. Provided Files 3.2.4. Internal Interfaces
3.2.3. Provided Files x
3.2.3.1. Directory Structure
3.2.4. Internal Interfaces x
3.2.4.1. Core Cache Interface (CCI-P) 3.2.4.2. Ethernet Interface 3.2.4.3. Ethernet MAC 3.2.4.4. 40G – 25G Gearbox 3.2.4.5. External Memory Interfaces 3.2.4.6. Ethernet MAC Wrapper Register Access
3.2.4.1. Core Cache Interface (CCI-P) x
3.2.4.1.1. FPGA Internal Register Access
3.2.4.5. External Memory Interfaces x
3.2.4.5.1. DDR4A and DDR4B 3.2.4.5.2. DDR4C 3.2.4.5.3. QDR4 Interface
4. Creating an N3000 FPGA Design x
4.1. Create New Project Directory 4.2. Create Your AFU Design Files 4.3. Build with make 4.4. Check Timing 4.5. Loading Your AFU into the Intel FPGA PAC N3000
4.2. Create Your AFU Design Files x
4.2.1. ccip_std_afu.sv 4.2.2. AFU File 4.2.3. QSF File 4.2.4. SDC File
4.5. Loading Your AFU into the Intel FPGA PAC N3000 x
4.5.1. Loading Your FPGA Image with JTAG 4.5.2. AFU Clocks 4.5.3. Creating an AFU with High Level Synthesis (HLS)
4.5.1. Loading Your FPGA Image with JTAG x
4.5.1.1. Preparing Your N3000 for JTAG 4.5.1.2. Disabling PCIe* Automatic Error Reporting (AER) 4.5.1.3. Using JTAG to Load the Intel® Arria® 10 *.sof file 4.5.1.4. How to Rescan PCIe* Bus and Re-enable PCIe* AER
4.5.2. AFU Clocks x
4.5.2.1. Hello AFU Example (uClk_usr) 4.5.2.2. Hello AFU Example (pll)
4.5.3. Creating an AFU with High Level Synthesis (HLS) x
4.5.3.1. Setting Up a Shell for HLS Development Work 4.5.3.2. Using the Initial Shell Design as a Shell 4.5.3.3. Compiling the Design and Producing a new N3000 FPGA Bitstream 4.5.3.4. Verifying Timing Constraints are Satisfied
5. Capturing Signals in AFU with Signal Tap x
5.1. Adding Signal Tap to the Design 5.2. Loading FPGA Image 5.3. Set Up Connections 5.4. How to Exit from the Debug Session 5.5. Troubleshooting Remote Debug Connections
1. About This Document
2. Introduction
3. High Level Description
4. Creating an N3000 FPGA Design
5. Capturing Signals in AFU with Signal Tap
6. Document Revision History for the Accelerator Functional Unit Developer Guide: Intel FPGA Programmable Acceleration Card N3000 Variants

3.2.4.6. Ethernet MAC Wrapper Register Access

Host processor access to Ethernet MAC Wrapper is by the CCI-P interface using MMIO indirect access as described in the FPGA Internal Register Access section. The RTL modules for register access are included in the encrypted portion of N3000 design and these modules must be included in your design.

There are two Ethernet MAC Wrappers where one wrapper is connected to the network and the other is connected to the Intel® Ethernet Controller XL710-BM2 NIC, as shown below:
Figure 20. Ethernet Wrapper Register Access
The Ethernet MAC Wrapper registers consist of the following:
  • CCI-P required Device Feature Header (DFH) and Information registers are located inside fpga_top.
  • Indirect access control register and status registers are located in phy_indir_wrap.
  • Ethernet MAC, PHY and multiplex/de-multiplex control and status registers are located in nfv_eth_wrapper.
For an example of how software accesses the Ethernet MAC wrapper, see the python source file included with the OPAE software release installation: 
inteldevstack/src/opae-*.*/usr/tools/extra/fpgadiag/fpgastats.py

The following description of registers below is provided for informational purposes. Do not change or modify this area code, but understanding how this works helps you create your AFU. When the lightweight mode is used, the Ethernet MAC registers are not included.

These registers are organized as follows:
Table 4.  Ethernet MAC Registers
Register Address Offset
ETH_GROUP_0_DFH 0x7000
ETH_GROUP_0_INFO 0x7008
ETH_GROUP_0_CTRL 0x7010
ETH_GROUP_0_STAT 0x7018
ETH_GROUP_1_DFH 0x8000
ETH_GROUP_1_INFO 0x8008
ETH_GROUP_1_CTRL 0x8010
ETH_GROUP_1_STAT 0x8018

The Information register consists of the following fields:

Table 5.  Information Register Fields
FIELD NAME RANGE ACCESS DEFAULT DESCRIPTION
Reserved [63:26] RsvdZ 0x0 Reserved
MAC light weight mode [25] RO 0x0

0 - MACs are in normal mode

1 - MACs are in light weight mode

Direction 24 RO 0x0

0 – XL710 side

1 - Network side
Speed_Gbs [23:16] RO 0xA Allowed: 10, 25, 40 Gbs.
NofPHYs [15:8] RO 0x8 Number of PHYs in group
GroupID [7:0] RO 0x0 Unique identifier of phy group. ETH_GROUP_0 = 0, ETH_GROUP_1 = 1

The indirect control field has one version for 10G mode and a second version for 25G and 40G mode. The 10G mode is shown below:

Table 6.  10G Indirect Control Field
FIELD NAME RANGE ACCESS DEFAULT DESCRIPTION
command [63:62] RW 0x0

Command:

0x0 - NOP

0x1 - RD request

0x2 - WR request
reserved [61:54] RO 0x0  
device select [53:49] RW 0x0

0x0 - Ethernet Wrapper regs select

0x2, 0x4, 0x6, 0x8, 0xA, 0xC, 0xE, 0x10 - PHY select

0x3, 0x5, 0x7, 0x9, 0xB, 0xD, 0xF, 0x11 - MAC select
PHY select device select = 0x2, 0x4, 0x6, 0x8, 0xA, 0xC, 0xE, 0x10
add features select [48] RW 0x0

0x0 - phy select

0x1 - reset controller / link status select
PHY Address/reset ctrl/link status [47:32] RW 0x0

add features select = 0x0:

PHY reconfiguration interface www.altera.com/literature/hb/arria-10/ug_arria10_xcvr_phy.pdf

add features select = 0x1: ref. to add features tab.
MAC register address [48:32] RW 0x0

When device select = 0x3, 0x5, 0x7, 0x9, 0xB, 0xD, 0xF, 0x11

This field is for Ethernet MAC IP registers as defined in:

www.altera.com/en_US/pdfs/literature/ug/ug_32b_10g_ethernet_mac.pdf.

ethernet wrapper regs address [48:32]

When device select = 0x0

This field includes Ethernet Mux/De-Mux registers
write data [31:0] RW 0x0 Write data for phy registers

For 25G and 40G mode:

Table 7.  25G and 40G Indirect Control Field
FIELD NAME RANGE ACCESS DEFAULT DESCRIPTION
command [63:62] RW 0x0

Command:

0x0 - NOP

0x1 - RD request

0x2 - WR request
reserved [61:54] RO 0x0  
device select [53:49] RW 0x0

0x0 - ethernet wrapper regs select

0x2, 0x4, 0x6, 0x8 - PHY select

0x3, 0x5, 0x7, 0x9 - MAC select
PHY select device select = 0x2, 0x4, 0x6, 0x8
add features select [48] RW 0x0

0x0 - phy select

0x1 - reset controller / link status select
PHY Address/reset ctrl/link status [47:32] RW 0x0

add features select = 0x0:

add features select = 0x1: ref. to add features tab.
MAC select device select = 0x3, 0x5, 0x7, 0x9
[48:32]  
Ethernet Wrapper regs address [48:32]

When device select = 0x0

This field includes Ethernet Mux/De-Mux registers
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