Accelerator Functional Unit Developer Guide: Intel FPGA Programmable Acceleration Card N3000 Variants

ID 683190
Date 7/15/2022
Document Table of Contents

2.1. Base Knowledge and Skills Prerequisites

The Intel® Acceleration Stack is an advanced application of FPGA technology. The platform-level complexity has been abstracted away for the AFU developer by the inclusion of all interfaces in the FPGA factory image and a standard Core Cache Interface (CCI-P) interface for host connectivity to your AFU.

This guide assumes the following FPGA logic design-related knowledge and skills:

  • FPGA compilation flows including the Intel® Quartus® Prime Pro Edition design flow.
  • Static Timing closure, including familiarity with the Timing Analyzer tool in Intel® Quartus® Prime Pro Edition, applying timing constraints, Synopsys* Design Constraints (.sdc) language and Tcl scripting, and design methods to close on timing critical paths.
  • RTL and coding practices to create synthesized logic.
  • High level synthesis (HLS) and Platform Designer design entry tools are supported.
  • RTL simulation tools.
  • Signal Tap Logic Analyzer tool in the Intel® Quartus® Prime Pro Edition software.