Accelerator Functional Unit Developer Guide: Intel FPGA Programmable Acceleration Card N3000 Variants

ID 683190
Date 7/15/2022
Document Table of Contents

3.2. N3000 Block Diagram

The board level N3000 block is shown below:
Figure 1.  N3000 Block Diagram

As can be seen in Figure 1, the Intel® Arria® 10 FPGA is central to data and control flow. Within the Intel® Arria® 10 FPGA, there are both data and control IP cores that are required for the board to work properly. You must include these required IP cores in your designs. Figure 2 illustrates the Intel® provided required and optional blocks as well as the ccip_std_afu block where your design is instantiated.

Figure 2.  ccip_std_afu Block