Accelerator Functional Unit Developer Guide: Intel FPGA Programmable Acceleration Card N3000 Variants

ID 683190
Date 7/15/2022
Document Table of Contents Setting Up a Shell for HLS Development Work

  1. Once the HLS is set up, set up the shell for a N3000 development environment and HLS.
    $ source <N3000 Install Directory>/inteldevstack/bin/
    $ source  <N3000 Install Directory>/inteldevstack/intelFPGA_pro/hls/
  2. You must have ModelSim installed and your PATH variable set to invoke vsim setup on your machine.
  3. Put Platform Designer version 19.2 in your PATH, using the following command:
    $ export PATH=$PATH: <N3000 Install Directory>/inteldevstack/intelFPGA_pro/\

    You are now ready to run the HLS example in this shell. You must use the above steps for future N3000 HLS development shell set up.

    The N3000 AFU design environment differs from the Intel® PAC with Intel® Arria® 10 GX FPGA:
    • N3000 uses a flat design with a static binary file rather than a partial reconfiguration.
    • N3000 does not support an ASE simulation environment.
    • N3000 does not support a Platform Interface Manager design flow.

    The N3000 HLS design flow is changed to accommodate these differences.