Accelerator Functional Unit Developer Guide: Intel FPGA Programmable Acceleration Card N3000 Variants

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ID 683190
Date 7/15/2022
Public
Document Table of Contents
Document Table of Contents x
1. About This Document 2. Introduction 3. High Level Description 4. Creating an N3000 FPGA Design 5. Capturing Signals in AFU with Signal Tap 6. Document Revision History for the Accelerator Functional Unit Developer Guide: Intel FPGA Programmable Acceleration Card N3000 Variants
1. About This Document x
1.1. Acronym List
2. Introduction x
2.1. Base Knowledge and Skills Prerequisites
2.1. Base Knowledge and Skills Prerequisites x
2.1.1. Considerations
3. High Level Description x
3.1. Steps for Creating Your AFU 3.2. N3000 Block Diagram 3.3. Factory Image Description
3.2. N3000 Block Diagram x
3.2.1. In-Line Data Path 3.2.2. Supported Ethernet Network Configurations 3.2.3. Provided Files 3.2.4. Internal Interfaces
3.2.3. Provided Files x
3.2.3.1. Directory Structure
3.2.4. Internal Interfaces x
3.2.4.1. Core Cache Interface (CCI-P) 3.2.4.2. Ethernet Interface 3.2.4.3. Ethernet MAC 3.2.4.4. 40G – 25G Gearbox 3.2.4.5. External Memory Interfaces 3.2.4.6. Ethernet MAC Wrapper Register Access
3.2.4.1. Core Cache Interface (CCI-P) x
3.2.4.1.1. FPGA Internal Register Access
3.2.4.5. External Memory Interfaces x
3.2.4.5.1. DDR4A and DDR4B 3.2.4.5.2. DDR4C 3.2.4.5.3. QDR4 Interface
4. Creating an N3000 FPGA Design x
4.1. Create New Project Directory 4.2. Create Your AFU Design Files 4.3. Build with make 4.4. Check Timing 4.5. Loading Your AFU into the Intel FPGA PAC N3000
4.2. Create Your AFU Design Files x
4.2.1. ccip_std_afu.sv 4.2.2. AFU File 4.2.3. QSF File 4.2.4. SDC File
4.5. Loading Your AFU into the Intel FPGA PAC N3000 x
4.5.1. Loading Your FPGA Image with JTAG 4.5.2. AFU Clocks 4.5.3. Creating an AFU with High Level Synthesis (HLS)
4.5.1. Loading Your FPGA Image with JTAG x
4.5.1.1. Preparing Your N3000 for JTAG 4.5.1.2. Disabling PCIe* Automatic Error Reporting (AER) 4.5.1.3. Using JTAG to Load the Intel® Arria® 10 *.sof file 4.5.1.4. How to Rescan PCIe* Bus and Re-enable PCIe* AER
4.5.2. AFU Clocks x
4.5.2.1. Hello AFU Example (uClk_usr) 4.5.2.2. Hello AFU Example (pll)
4.5.3. Creating an AFU with High Level Synthesis (HLS) x
4.5.3.1. Setting Up a Shell for HLS Development Work 4.5.3.2. Using the Initial Shell Design as a Shell 4.5.3.3. Compiling the Design and Producing a new N3000 FPGA Bitstream 4.5.3.4. Verifying Timing Constraints are Satisfied
5. Capturing Signals in AFU with Signal Tap x
5.1. Adding Signal Tap to the Design 5.2. Loading FPGA Image 5.3. Set Up Connections 5.4. How to Exit from the Debug Session 5.5. Troubleshooting Remote Debug Connections
1. About This Document
2. Introduction
3. High Level Description
4. Creating an N3000 FPGA Design
5. Capturing Signals in AFU with Signal Tap
6. Document Revision History for the Accelerator Functional Unit Developer Guide: Intel FPGA Programmable Acceleration Card N3000 Variants

4.2.1. ccip_std_afu.sv

The Initial_Shell_AFU includes ccip_std_afu.sv starting file where you can instantiate your AFU. Review of this file shows import ccip_if_pkg::* to include definitions of CCI-P interface structures. 
import ccip_if_pkg::*;  //required for CCI-P definitions
module ccip_std_afu #( …..
;
;
There is a CCI-P interface register to improve timing as shown below: 
    // =============================================================
    // Register SR <--> PR signals at interface before consuming it
    // =============================================================

    (* noprune *) logic [1:0]   pck_cp2af_pwrState_T1;
    (* noprune *) logic         pck_cp2af_error_T1;

    logic                       pck_cp2af_softReset_T1;
    t_if_ccip_Rx                pck_cp2af_sRx_T1;
    t_if_ccip_Tx                pck_af2cp_sTx_T0;

    // ============================================================= 
    // Register PR <--> PR signals near interface before consuming it
    // ============================================================= 
                                                     
    ccip_interface_reg inst_green_ccip_interface_reg  (              
        .pClk                           (pClk),                      
        .pck_cp2af_softReset_T0         (pck_cp2af_softReset),       
        .pck_cp2af_pwrState_T0          (pck_cp2af_pwrState),        
        .pck_cp2af_error_T0             (pck_cp2af_error),           
        .pck_cp2af_sRx_T0               (pck_cp2af_sRx),             
        .pck_af2cp_sTx_T0               (pck_af2cp_sTx_T0),          
                                                         
        .pck_cp2af_softReset_T1         (pck_cp2af_softReset_T1),    
        .pck_cp2af_pwrState_T1          (pck_cp2af_pwrState_T1),     
        .pck_cp2af_error_T1             (pck_cp2af_error_T1),        
        .pck_cp2af_sRx_T1               (pck_cp2af_sRx_T1),          
        .pck_af2cp_sTx_T1               (pck_af2cp_sTx)              
    );

Your AFU design connects to this registered CCI-P interface.

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