Accelerator Functional Unit Developer Guide: Intel FPGA Programmable Acceleration Card N3000 Variants

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ID 683190
Date 7/15/2022
Public
Document Table of Contents
Document Table of Contents x
1. About This Document 2. Introduction 3. High Level Description 4. Creating an N3000 FPGA Design 5. Capturing Signals in AFU with Signal Tap 6. Document Revision History for the Accelerator Functional Unit Developer Guide: Intel FPGA Programmable Acceleration Card N3000 Variants
1. About This Document x
1.1. Acronym List
2. Introduction x
2.1. Base Knowledge and Skills Prerequisites
2.1. Base Knowledge and Skills Prerequisites x
2.1.1. Considerations
3. High Level Description x
3.1. Steps for Creating Your AFU 3.2. N3000 Block Diagram 3.3. Factory Image Description
3.2. N3000 Block Diagram x
3.2.1. In-Line Data Path 3.2.2. Supported Ethernet Network Configurations 3.2.3. Provided Files 3.2.4. Internal Interfaces
3.2.3. Provided Files x
3.2.3.1. Directory Structure
3.2.4. Internal Interfaces x
3.2.4.1. Core Cache Interface (CCI-P) 3.2.4.2. Ethernet Interface 3.2.4.3. Ethernet MAC 3.2.4.4. 40G – 25G Gearbox 3.2.4.5. External Memory Interfaces 3.2.4.6. Ethernet MAC Wrapper Register Access
3.2.4.1. Core Cache Interface (CCI-P) x
3.2.4.1.1. FPGA Internal Register Access
3.2.4.5. External Memory Interfaces x
3.2.4.5.1. DDR4A and DDR4B 3.2.4.5.2. DDR4C 3.2.4.5.3. QDR4 Interface
4. Creating an N3000 FPGA Design x
4.1. Create New Project Directory 4.2. Create Your AFU Design Files 4.3. Build with make 4.4. Check Timing 4.5. Loading Your AFU into the Intel FPGA PAC N3000
4.2. Create Your AFU Design Files x
4.2.1. ccip_std_afu.sv 4.2.2. AFU File 4.2.3. QSF File 4.2.4. SDC File
4.5. Loading Your AFU into the Intel FPGA PAC N3000 x
4.5.1. Loading Your FPGA Image with JTAG 4.5.2. AFU Clocks 4.5.3. Creating an AFU with High Level Synthesis (HLS)
4.5.1. Loading Your FPGA Image with JTAG x
4.5.1.1. Preparing Your N3000 for JTAG 4.5.1.2. Disabling PCIe* Automatic Error Reporting (AER) 4.5.1.3. Using JTAG to Load the Intel® Arria® 10 *.sof file 4.5.1.4. How to Rescan PCIe* Bus and Re-enable PCIe* AER
4.5.2. AFU Clocks x
4.5.2.1. Hello AFU Example (uClk_usr) 4.5.2.2. Hello AFU Example (pll)
4.5.3. Creating an AFU with High Level Synthesis (HLS) x
4.5.3.1. Setting Up a Shell for HLS Development Work 4.5.3.2. Using the Initial Shell Design as a Shell 4.5.3.3. Compiling the Design and Producing a new N3000 FPGA Bitstream 4.5.3.4. Verifying Timing Constraints are Satisfied
5. Capturing Signals in AFU with Signal Tap x
5.1. Adding Signal Tap to the Design 5.2. Loading FPGA Image 5.3. Set Up Connections 5.4. How to Exit from the Debug Session 5.5. Troubleshooting Remote Debug Connections
1. About This Document
2. Introduction
3. High Level Description
4. Creating an N3000 FPGA Design
5. Capturing Signals in AFU with Signal Tap
6. Document Revision History for the Accelerator Functional Unit Developer Guide: Intel FPGA Programmable Acceleration Card N3000 Variants

5.3. Set Up Connections

  1. Set up a network connection between the instrumented FPGA AFU and your Signal Tap GUI. You can set the network connection based on whether you are using a remote or local debugging configuration. See diagram below illustrating the connection steps:
    Figure 44. Remote Debugging
    Figure 45. Local Debugging
  2. Use the OPAE tool mmlink to enable your host system for remote Signal Tap. This tool is included with the Intel® Acceleration Stack for the N3000
  3. Open a TCP port to accept incoming connection requests from remote debug hosts. 
    # mmlink -P 3333 –B 0xb2 Note, -B is the bus number of the target N3000 to connect
 ------- Command line Input START ---- 
 Segment : -1
 Bus : 02
 Device : -1
 Function : -1
 Socket-id : -1
 Port : 3333
 IP address : 0.0.0.0
 ------- Command line Input END ---- 
PORT Resource found.
Remote STP : Assert Reset
Remote STP : De-Assert Reset
Read signature value 53797343 to hw
Read version value 1 to hw
Read write fifo capacity value 32 to hw
m_listen: 4
listening on ip: 0.0.0.0; port: 3333

    You can debug remotely from a remote machine connected to your PAC host or you can debug on the local PAC host.

    • If debugging on a remote host:
      1. Make sure Intel® Quartus® Prime Pro Edition version 19.2 is installed and the directory $N3000_EXAMPLE_ROOT/hello_afu/hw/pac/remote_debug is copied to the remote host.
      2. Use System Console on the remote host to connect to the debug target host IP and TCP port using the following command:
        $ cd Remote host directory with $N3000_EXAMPLE_ROOT/hello_afu/hw/pac/\
remote_debug
$ system-console --rc_script=mmlink_setup_profiled.tcl \ 
remote_debug.sof <IP Address of target PAC host> 3333
        Note: You must have the System Console executable binary added to your PATH variable. The System Console executable binary is in the Intel® Quartus® Prime installation directory. An example of how to update your PATH variable is the following: 
        export PATH=$PATH:~/inteldevstack/intelFPGA_pro/quartus/sopc_builder/bin
    • If debugging on local host:
      1. Start System Console on the local host as shown below:
        $ # cd $N3000_EXAMPLE_ROOT/hello_afu/hw\
/pac/remote_debug 
$ system-console --rc_script=mmlink_setup_profiled.tcl \
remote_debug.sof localhost 3333
        Whether local or remote, the Intel® Quartus® Prime tool System Console starts a new GUI and runs the mmlink_setup_profiled.tcl setup script as shown below:

        The script takes 1-2 minutes to complete. When the “Remote system ready” message is displayed Signal Tap may be connected for debugging.

      2. Open Intel® Quartus® Prime GUI on the machine that is performing the debugging (i.e. local or remote host). In Intel® Quartus® Prime GUI, select File > Open and navigate to the hello_afu.stp file created in previous steps, select and open this file. The Signal Tap GUI comes up as shown below:
      3. In the Signal Tap GUI top right corner, “Hardware” pull down, where it says “Please Select”, click on the up/down arrows to bring up the hardware selection – select the choice that has System Console …. as shown below:

        The instance manager should show "Ready to acquire".

      4. Review the hello_afu.sv code and notice the following line:
      5. Enable the Signal Tap instance to capture data when cp2af_sRxPort.c0.mmioWrValid.
  4. Select the cp2af_sRxPort.co.mmioWrValid signal name, then right click the “Trigger Conditions” value and set this to 1 as shown below:
  5. Enable the hello_afu Signal Tap instance by entering F5.
  6. Modify the N3000 host application to add a shared connection to the FPGA in order to create host transactions that can cause the hello_afu STP interface to activate. This shared connection allows the Signal Tap and host communication to be shared through the PCIe* bus.
    1. Edit $N3000_EXAMPLE_ROOT/hello_afu/hw/afu/sw/hello_afu.c to change the following line from:
      res = fpgaOpen(afc_token, &afc_h, 0);
      To; 
      res = fpgaOpen(afc_token, &afc_h, FPGA_OPEN_SHARED);
    2. Save hello_afu.c and build the code
      $ make
    3. Run the hello_afu host code as root or sudo as shown below:
      # ./hello_afu 
Running Test
AFU DFH REG = 1000010000000000
AFU ID LO = 9722d43375b61c66
AFU ID HI = 850adcc26ceb4b22
AFU NEXT = 00000000
AFU RESERVED = 00000000
Reading Scratch Register (Byte Offset=00000080) = 00000000
MMIO Write to Scratch Register (Byte Offset=00000080) = 123456789abcdef
Reading Scratch Register (Byte Offset=00000080) = 123456789abcdef
Setting Scratch Register (Byte Offset=00000080) = 00000000
Reading Scratch Register (Byte Offset=00000080) = 00000000
Done Running Test
    Your Signal Tap instance captures the write transactions as shown below:
Level Two Title