Accelerator Functional Unit Developer Guide: Intel FPGA Programmable Acceleration Card N3000 Variants

ID 683190
Date 7/15/2022
Document Table of Contents

4.4. Check Timing

Verify your compiled design meets timing and power requirements by performing the following steps:

  1. Go to the "Tasks" pane and select “Compilation Report”.
    Figure 24. Compilation Report
  2. Under Timing Analyzer, verify no failing timing paths.
    Figure 25. Timing Analyzer

    You can safely ignore the "Unconstrained Paths" report in this release.

  3. Select Power Analyzer and check that “Total Thermal Power Dissipation” is within the thermal characteristics of your server air flow.
  4. Check the Thermal Specifications section of the N3000 Data Sheet.
    The power results shown in the power analyzer are based on the worst case FPGA junction temperature of 100° C.
    Figure 26. Power Analyzer Summary
  5. Select Project > Generate Early Power Estimator File to perform additional power analysis in the Intel® Arria® 10 Early Power Estimator by clicking on this download .
    For more information, refer to the Early Power Estimator for Intel® Arria® 10 FPGAs User Guide.
    The Early Power Estimator (EPE) file can take a few minutes to generate. The default EPE file location is /prj/pac_baseline/chip_early_pwr.csv. This .csv file can be imported into the Early Power Estimator for detailed analysis of power consumption of your design.
    Figure 27. Generate Early Power Estimator File