Accelerator Functional Unit Developer Guide: Intel FPGA Programmable Acceleration Card N3000 Variants

ID 683190
Date 7/15/2022
Document Table of Contents

3.1. Steps for Creating Your AFU

The following steps are suggested for designing a custom FPGA application for the N3000:

  1. Become familiar with the board and FPGA block diagrams, interfaces and code provided within the N3000 factory image.
  2. Review the Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual. You must follow the interface requirements and include required registers in your design for proper N3000 operation.
    In addition, the OPAE Basic Building Blocks wiki provides CCI-P tutorials and basic building blocks (BBB) for interfacing your AFU. You are strongly encouraged to review this resource. The Memory Properties Factory BBB is an essential component for transaction ordering in AFUs requiring more complex host interfacing functions.
  3. Define and plan your FPGA application.
  4. Copy the Initial_Shell_AFU files and directory structure. This directory structure is the starting point for your design.
  5. Implement your FPGA application. You can use one or a combination of the following design entry methods:
    1. RTL (System Verilog/VHDL)
    2. Platform Designer
    3. HLS
    Note: Existing design blocks can be added as required.
  6. Implement host software code.
  7. Simulate your design at the unit level.
  8. Create timing constraints files.
  9. Update the Intel® Quartus® Prime Settings File (afu.qsf) to add your new blocks.
  10. Compile, synthesize, place and route your new design using provided makefile.
  11. Validate timing closure.
  12. Validate power consumption.
  13. The provided makefile compilation script includes a post-compilation script that creates a raw binary file.
  14. The raw binary file is used as an input to the Intel® Acceleration Stack utility PACSign. PACSign adds a required header to the raw binary file. The output file from PACSign is validated by the N3000 Intel® MAX® 10 Root of Trust for storage in the N3000 flash storage.
  15. Flash the binary file produced by PACSign into FPGA flash using fpgasupdate.
  16. Use the rsu utility to load the new FPGA binary file from flash into the FPGA.
  17. If needed, use the Signal Tap tool to diagnose and resolve issues.