Accelerator Functional Unit Developer Guide: Intel FPGA Programmable Acceleration Card N3000 Variants

ID 683190
Date 7/15/2022
Document Table of Contents

3.3. Factory Image Description

The N3000 provides an example design that demonstrates usage of the key interfaces available to the ccip_std_afu module.

The block diagram of each network configuration is shown below:

Figure 21. Factory Image Block Diagram for 8x10 GbE
Figure 22. Factory Image Block Diagram for 2x2x25GbE
Figure 23. Factory Image Block Diagram for 4x25 GbE
The Factory Images include the following high level functions:
  • Memory-to-memory DMA blocks illustrating host to and from external memory transfers. For more information about this component, refer to the DMA Accelerator Functional Unit (AFU) User Guide: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA .
  • Native Loopback to test memory reads and writes, bandwidth, and latency. For more information, refer to the Native Loopback Accelerator Functional Unit (AFU) User Guide.
  • Aggregated Ethernet interface
  • Required board management functions