Accelerator Functional Unit Developer Guide: Intel FPGA Programmable Acceleration Card N3000 Variants

ID 683190
Date 7/15/2022
Public
Document Table of Contents

3.2.4.3. Ethernet MAC

The 25 GbE MAC IP core is documented in the 25G Ethernet Intel® Arria® 10 FPGA IP User Guide. The N3000 configures the 25 GbE MACwith the following parameters set:

Table 2.  25G MAC IP Setting
Parameter IP Core parameter setting

Ready Latency

0

Enable RS-FEC

Off

Enable flow control

On

Enable link fault generation

On

Enable preamble pass through

Off

Enable TX CRC pass through

Off

Enable MAC statistics counters

On

Off for Light weight mode

Enable IEEE 1588

Off

The Intel C827 Re-timer performs FEC functionality, therefore the A10 Ethernet MAC does not have RS-FEC enabled.

The 10 GbE MAC IP core is documented in: Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide

The 40 GbE MAC IP core is documented in: Low Latency 40-Gbps Ethernet IP Core User Guide

The 40 and 10 GbE MAC IP core are set with the following parameters:

Table 3.  40G MAC IP Setting

Parameter

IP core parameter setting

Enable SyncE

Off

PHY reference

644.53125MHz

Use external TX MAC PLL

On

Flow control mode

Standard flow control

Average inter-packet gap

12

Enable 1588 PTP

Off

Enable link fault generation

On

Enable TX CRC insertion

On

Enable preamble pass through

Off

Enable alignment EOP on FCS word

On

Enable TX statistics

On

Enable RX statistics

On

Enable strict SFD checking

Off