AXI Multichannel DMA Intel® FPGA IP for PCI Express* User Guide

ID 817911
Date 7/22/2024
Public

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Document Table of Contents

4.3. Resets

Table 12.  Resets
Signal Name Direction Description
axi_st_areset_n Input Reset signal for AXI Streaming interface
axi_mm_areset_n Input Reset signal for AXI-MM interface
axi_lite_areset_n Input Reset signal for AXI-Lite interface