AXI Multichannel DMA Intel® FPGA IP for PCI Express* User Guide

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ID 817911
Date 7/22/2024
Public
Document Table of Contents
Document Table of Contents x
1. About This Document 2. Introduction 3. Functional Description 4. Interfaces 5. Parameters 6. Designing with the IP Core 7. Known Issues 8. Revision History for the AXI Multichannel DMA Intel® FPGA IP for PCI Express* User Guide
1. About This Document x
1.1. Intended Audience 1.2. Conventions 1.3. Terms and Acronyms 1.4. Related Information
2. Introduction x
2.1. Overview 2.2. IP Features 2.3. Device Family Support 2.4. IP and Design Example Support 2.5. Recommended Speed Grade 2.6. Resource Utilization 2.7. Release Information
2.2. IP Features x
2.2.1. Root Port Mode Features 2.2.2. Endpoint Mode Features
4. Interfaces x
4.1. System Block Diagram 4.2. Clocks 4.3. Resets 4.4. PCIe IP-facing Interfaces 4.5. User-facing Interfaces
4.4. PCIe IP-facing Interfaces x
4.4.1. PCIe AXI-ST TX Interface (ss_tx_st) 4.4.2. PCIe AXI-ST RX Interface (ss_rx_st) 4.4.3. Control and Status Register Interface (ss_csr_lite) 4.4.4. Flow Control Credit Interface 4.4.5. Configuration Intercept Interface (CII) 4.4.6. Completion Timeout Interface (ss_cplto) 4.4.7. Function Level Reset Interface 4.4.8. Control Shadow Interface (ss_ctrlshadow)
4.4.4. Flow Control Credit Interface x
4.4.4.1. Transmit Flow Credit Interface (ss_txcrdt) 4.4.4.2. Receive Flow Control Credit Interface (ss_rxcrdt)
4.4.5. Configuration Intercept Interface (CII) x
4.4.5.1. Configuration Intercept Request Interface (ss_cii_req) 4.4.5.2. Configuration Intercept Response Interface (ss_cii_resp)
4.4.7. Function Level Reset Interface x
4.4.7.1. FLR Received Interface (ss_flrrcvd) 4.4.7.2. FLR Completion Interface (ss_flrcmpl)
4.5. User-facing Interfaces x
4.5.1. H2D AXI-ST Source (h2d_st_initatr) 4.5.2. D2H AXI-ST Sink (d2h_st_respndr) 4.5.3. BAM AXI-MM Master (bam_mm_initatr) 4.5.4. BAS AXI-MM Slave (bas_mm_respndr) 4.5.5. PIO AXI-Lite Master (pio_lite_initiatr) 4.5.6. HIP Reconfig AXI-Lite Slave (user_csr_lite) 4.5.7. User Event MSI-X (user_msix) 4.5.8. User Event MSI (user_msi) 4.5.9. User Function Level Reset (user_flr) 4.5.10. User Configuration Intercept Interface - EP Only 4.5.11. Configuration Slave (cs_lite_respndr) - RP Only
4.5.10. User Configuration Intercept Interface - EP Only x
4.5.10.1. User Configuration Intercept Request Interface (user_cii_req) 4.5.10.2. User Configuration Intercept Response Interface (user_cii_resp)
5. Parameters x
5.1. IP Settings 5.2. PCIe Settings 5.3. Design Examples
5.2. PCIe Settings x
5.2.1. MCDMA Settings 5.2.2. PCI Express / PCI Capabilities 5.2.3. Base Address Registers
5.2.1. MCDMA Settings x
5.2.1.1. Multichannel DMA Mode 5.2.1.2. Bursting Master Mode 5.2.1.3. Bursting Slave Mode 5.2.1.4. BAM+BAS Mode 5.2.1.5. BAM+MCDMA Mode 5.2.1.6. BAM+BAS+MCDMA Mode
5.2.2. PCI Express / PCI Capabilities x
5.2.2.1. PCIe Device 5.2.2.2. PCIe MSI-X
5.2.2.2. PCIe MSI-X x
5.2.2.2.1. PCIe PF MSI-X 5.2.2.2.2. PCIe VF MSI-X
6. Designing with the IP Core x
6.1. Generating the IP Core 6.2. IP Core Generation Output 6.3. Simulating the IP Core 6.4. Quick Start Guide
6.4. Quick Start Guide x
6.4.1. Functional Description 6.4.2. Generating the Design Example 6.4.3. Simulating the Design Example 6.4.4. Testing the Design Example
1. About This Document
2. Introduction
3. Functional Description
4. Interfaces
5. Parameters
6. Designing with the IP Core
7. Known Issues
8. Revision History for the AXI Multichannel DMA Intel® FPGA IP for PCI Express* User Guide

4.4.3. Control and Status Register Interface (ss_csr_lite)

The AXI MCDMA IP uses this interface to access registers implemented in the AXI Streaming Intel FPGA IP for PCI Express module, allowing the user application to access PCIe config space registers of all Functions as well as soft register space registers implemented in the AXI Streaming IP.

Application access PCIe config space registers through this interface by adding offset of 0x80000 to the actual physical address of PCIe config space address. Refer to the Register Address Map in the AXI Streaming Intel FPGA IP for PCI Express User Guide.

Along with PCIe configuration access, this interface is also used for application error reporting, allowing application to indicate various errors. User Application must write to error generation control registers through this interface to send error information to the PCIe Hard IP block. For more information, refer to the section Application Error Reporting in the AXI Streaming Intel FPGA IP for PCI Express User Guide.

The interface follows AXI4-Lite protocol.

Interface clock: axi_lite_clk

Table 15.  Control and Status Register Interface
Signal Name Direction Description
Write Address Channel
app_ss_lite_csr_awvalid Output

Indicates that the write address channel signals are valid.
ss_app_lite_csr_awready Input

Indicates that a transfer on the write address channel can be accepted.
app_ss_lite_csr_awaddr[19:0] Output

The address of the first transfer in awrite transaction.
Write Data Channel
app_ss_lite_csr_wvalid Output

Indicates that the write data channel signals are valid.
ss_app_lite_csr_wready Input

Indicates that a transfer on the write data channel can be accepted.
app_ss_lite_csr_wdata[31:0] Output

Write data.

app_ss_lite_csr_wstrb[3:0] Output

Write strobe, indicate which byte lanes hold valid data.

Write Response Channel
ss_app_lite_csr_bvalid Input

Indicates that the write response channel signals are valid.
app_ss_lite_csr_bready Output

Indicates that a transfer on the write response channel can be accepted.
ss_app_lite_csr_bresp[1:0] Input

Write response, indicates the status of a write transaction.
Read Address Channel
app_ss_lite_csr_arvalid Output

Indicates that the read address channel signals are valid.
ss_app_lite_csr_arready Input

Indicates that a transfer on the read address channel can be accepted.
app_ss_lite_csr_araddr[19:0] Output

The address of the first transfer in a read transaction.
Read Data Channel
ss_app_lite_csr_rvalid Input

Indicates that the read data channel signals are valid.
app_ss_lite_csr_rready Output

Indicates that a transfer on the read data channel can be accepted.
ss_app_lite_csr_rdata[31:0] Input

Read data.

ss_app_lite_csr_rresp[1:0] Input

Read response, indicates the status of a read transfer.
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