AXI Multichannel DMA Intel® FPGA IP for PCI Express* User Guide

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ID 817911
Date 7/22/2024
Public
Document Table of Contents
Document Table of Contents x
1. About This Document 2. Introduction 3. Functional Description 4. Interfaces 5. Parameters 6. Designing with the IP Core 7. Known Issues 8. Revision History for the AXI Multichannel DMA Intel® FPGA IP for PCI Express* User Guide
1. About This Document x
1.1. Intended Audience 1.2. Conventions 1.3. Terms and Acronyms 1.4. Related Information
2. Introduction x
2.1. Overview 2.2. IP Features 2.3. Device Family Support 2.4. IP and Design Example Support 2.5. Recommended Speed Grade 2.6. Resource Utilization 2.7. Release Information
2.2. IP Features x
2.2.1. Root Port Mode Features 2.2.2. Endpoint Mode Features
4. Interfaces x
4.1. System Block Diagram 4.2. Clocks 4.3. Resets 4.4. PCIe IP-facing Interfaces 4.5. User-facing Interfaces
4.4. PCIe IP-facing Interfaces x
4.4.1. PCIe AXI-ST TX Interface (ss_tx_st) 4.4.2. PCIe AXI-ST RX Interface (ss_rx_st) 4.4.3. Control and Status Register Interface (ss_csr_lite) 4.4.4. Flow Control Credit Interface 4.4.5. Configuration Intercept Interface (CII) 4.4.6. Completion Timeout Interface (ss_cplto) 4.4.7. Function Level Reset Interface 4.4.8. Control Shadow Interface (ss_ctrlshadow)
4.4.4. Flow Control Credit Interface x
4.4.4.1. Transmit Flow Credit Interface (ss_txcrdt) 4.4.4.2. Receive Flow Control Credit Interface (ss_rxcrdt)
4.4.5. Configuration Intercept Interface (CII) x
4.4.5.1. Configuration Intercept Request Interface (ss_cii_req) 4.4.5.2. Configuration Intercept Response Interface (ss_cii_resp)
4.4.7. Function Level Reset Interface x
4.4.7.1. FLR Received Interface (ss_flrrcvd) 4.4.7.2. FLR Completion Interface (ss_flrcmpl)
4.5. User-facing Interfaces x
4.5.1. H2D AXI-ST Source (h2d_st_initatr) 4.5.2. D2H AXI-ST Sink (d2h_st_respndr) 4.5.3. BAM AXI-MM Master (bam_mm_initatr) 4.5.4. BAS AXI-MM Slave (bas_mm_respndr) 4.5.5. PIO AXI-Lite Master (pio_lite_initiatr) 4.5.6. HIP Reconfig AXI-Lite Slave (user_csr_lite) 4.5.7. User Event MSI-X (user_msix) 4.5.8. User Event MSI (user_msi) 4.5.9. User Function Level Reset (user_flr) 4.5.10. User Configuration Intercept Interface - EP Only 4.5.11. Configuration Slave (cs_lite_respndr) - RP Only
4.5.10. User Configuration Intercept Interface - EP Only x
4.5.10.1. User Configuration Intercept Request Interface (user_cii_req) 4.5.10.2. User Configuration Intercept Response Interface (user_cii_resp)
5. Parameters x
5.1. IP Settings 5.2. PCIe Settings 5.3. Design Examples
5.2. PCIe Settings x
5.2.1. MCDMA Settings 5.2.2. PCI Express / PCI Capabilities 5.2.3. Base Address Registers
5.2.1. MCDMA Settings x
5.2.1.1. Multichannel DMA Mode 5.2.1.2. Bursting Master Mode 5.2.1.3. Bursting Slave Mode 5.2.1.4. BAM+BAS Mode 5.2.1.5. BAM+MCDMA Mode 5.2.1.6. BAM+BAS+MCDMA Mode
5.2.2. PCI Express / PCI Capabilities x
5.2.2.1. PCIe Device 5.2.2.2. PCIe MSI-X
5.2.2.2. PCIe MSI-X x
5.2.2.2.1. PCIe PF MSI-X 5.2.2.2.2. PCIe VF MSI-X
6. Designing with the IP Core x
6.1. Generating the IP Core 6.2. IP Core Generation Output 6.3. Simulating the IP Core 6.4. Quick Start Guide
6.4. Quick Start Guide x
6.4.1. Functional Description 6.4.2. Generating the Design Example 6.4.3. Simulating the Design Example 6.4.4. Testing the Design Example
1. About This Document
2. Introduction
3. Functional Description
4. Interfaces
5. Parameters
6. Designing with the IP Core
7. Known Issues
8. Revision History for the AXI Multichannel DMA Intel® FPGA IP for PCI Express* User Guide

4.5.5. PIO AXI-Lite Master (pio_lite_initiatr)

The PIO Master is enabled in Multichannel DMA mode. It bypasses the DMA block and provides a way for the Host to do MMIO read/write to CSR registers of user logic. PCIe BAR2 is mapped to the PIO Master. Any TLP targeting BAR2 is forwarded to the user logic via AXI-Lite interface. TLP address targeting the PIO interface should be 8 bytes aligned. The PIO interface supports non-bursting 64-bit write and read transfers only.

Note: Do not attempt to perform 32-bit transactions on PIO interface. Only 64-bit transactions are supported.
The PIO interface address mapping is as follows: 
PIO address = {vf_active, pf[PF_NUM_W-1:0], vf[VF_NUM_W-1:0], address}
  1. vf_active: This indicates that SRIOV is enabled
  2. pf[PF_NUM_W-1:0]: This denotes the physical function number decoded from the PCIe header. PF_NUM_W, which is defined as ($clog2(Number of PFs)) is a parameter in the RTL design chosen to limit the number of wires on the user interface of the Multichannel DMA IP. This reduces the overhead associated with unnecessary wiring.
  3. vf[VF_NUM_W-1:0]: This denotes the virtual function number decoded from the PCIe header. VF_NUM_W, which is defined as ($clog2(Number of VFs)) is a parameter in the RTL design chosen to limit the number of wires on the user interface of the Multichannel DMA IP. This reduces the overhead associated with unnecessary wiring.
  4. address: Number of bits required for BAR2 size requested across all Functions (PFs and VFs). Example: If BAR2 is selected as 4 MB, the address size is 22 bits.

The following table describes the interface signals.

Interface clock: axi_lite_clk

Table 28.  PIO AXI-Lite Master Interface
Signal Name Direction Description
Write Address Channel
rx_pio_axi_lite_awvalid Output

Write address valid
rx_pio_axi_lite_awready Input

Write address ready

Indicates that the slave is ready to accept an address.
rx_pio_axi_lite_awaddr[n:0] Output

Write address.

The write address gives the address of the first transfer in a write burst transaction.

Refer to the PIO address mapping for actual address width.
rx_pio_axi_lite_awprot[2:0] Output

Protection type.

This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access. (not used)

Write Data Channel
rx_pio_axi_lite_wvalid Output

Write data valid
rx_pio_axi_lite_wready Input

Write data ready

Indicates that the slave is ready to accept data
rx_pio_axi_lite_wdata[63:0] Output

Write data
rx_pio_axi_lite_wstrb[7:0] Output

Write strobe

Indicates which byte lanes hold valid data
Write Response Channel
rx_pio_axi_lite_bvalid Input

Indicates that the write response channel signals are valid
rx_pio_axi_lite_bready Output

Indicates that a transfer on the write response channel can be accepted
rx_pio_axi_lite_bresp[1:0] Input

Write response

Indicates the status of a write transaction
Read Address Channel
rx_pio_axi_lite_arvalid Output

Indicates that the read address channel signals are valid
rx_pio_axi_lite_arready Input

Indicates that a transfer on the read address channel can be accepted

rx_pio_axi_lite_araddr[n:0] Output

The address of the first transfer in a read transaction.

Refer to the PIO address mapping for actual address width.
rx_pio_axi_lite_arprot[2:0] Output

Protection type.

This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access. (not used)

Read Data Channel
rx_pio_axi_lite_rvalid Input

Read data valid
rx_pio_axi_lite_rready Output

Indicates the master is ready to accept read data
rx_pio_axi_lite_rdata[63:0] Input

Read data
rx_pio_axi_lite_rresp[1:0] Input

Read response, indicates the status of the read transfer.

EXOKAY is not supported on Intel FPGA.

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