AXI Multichannel DMA Intel® FPGA IP for PCI Express* User Guide

Download PDF
ID 817911
Date 7/22/2024
Public
Document Table of Contents
Document Table of Contents x
1. About This Document 2. Introduction 3. Functional Description 4. Interfaces 5. Parameters 6. Designing with the IP Core 7. Known Issues 8. Revision History for the AXI Multichannel DMA Intel® FPGA IP for PCI Express* User Guide
1. About This Document x
1.1. Intended Audience 1.2. Conventions 1.3. Terms and Acronyms 1.4. Related Information
2. Introduction x
2.1. Overview 2.2. IP Features 2.3. Device Family Support 2.4. IP and Design Example Support 2.5. Recommended Speed Grade 2.6. Resource Utilization 2.7. Release Information
2.2. IP Features x
2.2.1. Root Port Mode Features 2.2.2. Endpoint Mode Features
4. Interfaces x
4.1. System Block Diagram 4.2. Clocks 4.3. Resets 4.4. PCIe IP-facing Interfaces 4.5. User-facing Interfaces
4.4. PCIe IP-facing Interfaces x
4.4.1. PCIe AXI-ST TX Interface (ss_tx_st) 4.4.2. PCIe AXI-ST RX Interface (ss_rx_st) 4.4.3. Control and Status Register Interface (ss_csr_lite) 4.4.4. Flow Control Credit Interface 4.4.5. Configuration Intercept Interface (CII) 4.4.6. Completion Timeout Interface (ss_cplto) 4.4.7. Function Level Reset Interface 4.4.8. Control Shadow Interface (ss_ctrlshadow)
4.4.4. Flow Control Credit Interface x
4.4.4.1. Transmit Flow Credit Interface (ss_txcrdt) 4.4.4.2. Receive Flow Control Credit Interface (ss_rxcrdt)
4.4.5. Configuration Intercept Interface (CII) x
4.4.5.1. Configuration Intercept Request Interface (ss_cii_req) 4.4.5.2. Configuration Intercept Response Interface (ss_cii_resp)
4.4.7. Function Level Reset Interface x
4.4.7.1. FLR Received Interface (ss_flrrcvd) 4.4.7.2. FLR Completion Interface (ss_flrcmpl)
4.5. User-facing Interfaces x
4.5.1. H2D AXI-ST Source (h2d_st_initatr) 4.5.2. D2H AXI-ST Sink (d2h_st_respndr) 4.5.3. BAM AXI-MM Master (bam_mm_initatr) 4.5.4. BAS AXI-MM Slave (bas_mm_respndr) 4.5.5. PIO AXI-Lite Master (pio_lite_initiatr) 4.5.6. HIP Reconfig AXI-Lite Slave (user_csr_lite) 4.5.7. User Event MSI-X (user_msix) 4.5.8. User Event MSI (user_msi) 4.5.9. User Function Level Reset (user_flr) 4.5.10. User Configuration Intercept Interface - EP Only 4.5.11. Configuration Slave (cs_lite_respndr) - RP Only
4.5.10. User Configuration Intercept Interface - EP Only x
4.5.10.1. User Configuration Intercept Request Interface (user_cii_req) 4.5.10.2. User Configuration Intercept Response Interface (user_cii_resp)
5. Parameters x
5.1. IP Settings 5.2. PCIe Settings 5.3. Design Examples
5.2. PCIe Settings x
5.2.1. MCDMA Settings 5.2.2. PCI Express / PCI Capabilities 5.2.3. Base Address Registers
5.2.1. MCDMA Settings x
5.2.1.1. Multichannel DMA Mode 5.2.1.2. Bursting Master Mode 5.2.1.3. Bursting Slave Mode 5.2.1.4. BAM+BAS Mode 5.2.1.5. BAM+MCDMA Mode 5.2.1.6. BAM+BAS+MCDMA Mode
5.2.2. PCI Express / PCI Capabilities x
5.2.2.1. PCIe Device 5.2.2.2. PCIe MSI-X
5.2.2.2. PCIe MSI-X x
5.2.2.2.1. PCIe PF MSI-X 5.2.2.2.2. PCIe VF MSI-X
6. Designing with the IP Core x
6.1. Generating the IP Core 6.2. IP Core Generation Output 6.3. Simulating the IP Core 6.4. Quick Start Guide
6.4. Quick Start Guide x
6.4.1. Functional Description 6.4.2. Generating the Design Example 6.4.3. Simulating the Design Example 6.4.4. Testing the Design Example
1. About This Document
2. Introduction
3. Functional Description
4. Interfaces
5. Parameters
6. Designing with the IP Core
7. Known Issues
8. Revision History for the AXI Multichannel DMA Intel® FPGA IP for PCI Express* User Guide

4.5.3. BAM AXI-MM Master (bam_mm_initatr)

The BAM bypasses the AXI MCDMA IP for PCI Express and provides a way for a Host to perform bursting PIO read/writes to the user logic. The BAM converts memory read and write TLPs initiated by the remote link partner and received over the PCIe link into AXI-MM burst read and write transactions, and sends back CplD TLPs for read requests it receives.

The BAM interface address mapping is as follows:

BAM address = {vf_active, pf[PF_NUM_W-1:0], vf[VF_NUM_W-1:0], bar_num[2:0], address}

  1. vf_active: This indicates that SRIOV is enabled.
  2. pf[PF_NUM_W-1:0]: This denotes the physical function number decoded from the PCIe header. PF_NUM_W, which is defined as ($clog2(Number of PFs)) is a parameter in the RTL design chosen to limit the number of wires on the user interface of the Multichannel DMA IP. This reduces the overhead associated with unnecessary wiring.
  3. vf[VF_NUM_W-1:0]: This denotes the virtual function number decoded from the PCIe header. VF_NUM_W, which is defined as ($clog2(Number of VFs)) is a parameter in the RTL design chosen to limit the number of wires on the user interface of the Multichannel DMA IP. This reduces the overhead associated with unnecessary wiring.
  4. bar_num[2:0]: This denotes the BAR number decoded from the PCIe header.
  5. address: Number of bits required for BAR2 size requested across all Functions (PFs and VFs). Example: If BAR2 is selected as 4 MB, the address size is 22 bits.

Interface Clock: axi_mm_clk

DWIDTH:
  • 1024 bits for Gen5 1x16
  • 512 bits for Gen5 2x8, Gen4 1x16, Gen3 1x16
  • 256 bits for Gen4 2x8, Gen3 2x8
Note: For the Root Port: In the Root Port mode, the AXI-MM address output from BAM is the same as the one received on the PCIe AXI-ST RX Interface (st_rx).
Table 26.  BAM AXI-MM Master Interface
Signal Name Direction Description
Write Address Channel
bam_axi_mm_awvalid Output

Write address valid.

This signal indicates that the channel is signaling valid write address and control information.

bam_axi_mm_awready Input

Write address ready.

This signal indicates that the slave is ready to accept an address and associated control signals.

bam_axi_mm_awid[3:0] Output

Write address ID.

This signal is the identification tag for the write address group of signals. The default value is 0.

bam_axi_mm_awaddr[n:0] Output

Write address.

The write address gives the address of the first transfer in a write burst transaction.

Refer to the BAM address mapping for the actual address width.
bam_axi_mm_awlen[7:0] Output

Burst length.

The burst length gives the exact number of transfers in a burst.

This information determines the number of data transfers associated with the address.

bam_axi_mm_awsize[2:0] Output

Burst size.

This signal indicates the size of each transfer in the burst.

bam_axi_mm_awburst[1:0] Output

Burst type.

The burst type and the size information determine how the address for each transfer within the burst is calculated. The Intel FPGA supports only the INCR burst type.

bam_axi_mm_awlock Output Lock type.

Tied to '0'.
bam_axi_mm_awprot[2:0] Output

Protection type.

This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access. (not used)

Write Data Channel
bam_axi_mm_wvalid Output

Write Data Valid
bam_axi_mm_wready Input

Write Data Ready

Indicates the receiver can accept write data
bam_axi_mm_wdata[DWIDTH-1:0] Output

Write data
bam_axi_mm_wstrb[DWIDTH/8-1:0] Output

Write strobes
bam_axi_mm_wlast Output

Write last
Write Response Channel
bam_axi_mm_bvalid Input

Write Response Valid
bam_axi_mm_bready Output

Write Response Ready
bam_axi_mm_bid[3:0] Input

Response ID

This signal is the ID tag of the write response.

bam_axi_mm_bresp[1:0] Input

Write Response
Read Address Channel
bam_axi_mm_arvalid Output

Read address valid. This signal indicates that the channel is signaling valid read address and control information.

bam_axi_mm_arready Input

Read address ready. This signal indicates that the slave is ready to accept an address and associated control signals

bam_axi_mm_arid[3:0] Output

Read address ID. This signal is the identification tag for the read address group of signals. The default value is 0.

bam_axi_mm_araddr[n:0] Output

Read address. The read address gives the address of the first transfer in a read burst transaction.

Refer to the BAM address mapping for the actual address width.
bam_axi_mm_arlen[7:0] Output

Burst length. The burst length gives the exact number of transfers in a burst.

bam_axi_mm_arsize[2:0] Output

Burst size. This signal indicates the size of each transfer in the burst.

bam_axi_mm_arburst[1:0] Output Burst type.

The burst type and the size information determine how the address for each transfer within the burst is calculated. The Intel FPGA supports only the INCR burst type.

bam_axi_mm_arlock Output Lock type.

Tied to '0'.
bam_axi_mm_arprot[2:0] Output

Protection type.

This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access. (not used)

Read Data Channel
bam_axi_mm_rvalid Input

Read data valid.

This signal indicates that the channel is signaling the read data is valid.

bam_axi_mm_rready Output

Read data ready.

This signal indicates that the master can accept the read data and response information.

bam_axi_mm_rid[3:0] Input

Read ID tag.

This signal is the identification tag for the read data group of signals generated by the slave.

bam_axi_mm_rdata[DWIDTH-1:0] Input

Read Data
bam_axi_mm_rresp[1:0] Input

Read response.

This signal indicates the status of the read transfer. EXOKAY is not supported on Intel FPGA. (Per the AXI specification, EXOKAY means the Exclusive read succeeded. This response is only permitted for an Exclusive read).
  • 2'b00: OKAY
  • 2'b01: EXOKAY
  • 2'b10: SLVERR
  • 2'b11: DECERR
bam_axi_mm_rlast Input

Read last.

This signal indicates the last transfer in a read burst.
Level Two Title