Ethernet Subsystem Intel® FPGA IP User Guide: Early Access Customer Release

ID 773413
Date 4/14/2023

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Document Table of Contents

9.1. Steps to Generate the Example Design

  1. Create project
  2. Open IP GUI
  3. Configure the IP for your supported variant
  4. Open the Example Design Tab
    1. Select Single instance of IP core
    2. Select Simulation checkbox for simulating the example design
    3. Select Synthesis checkbox for synthesizing the example design
    4. Select either Verilog or VHDL for generated file format
    5. Select the appropriate development kit. If you aren’t using a development kit, choose None
  5. Click on Generate Example Design
  6. Select the desired directory to generate the example design in