Ethernet Subsystem Intel® FPGA IP User Guide: Early Access Customer Release

ID 773413
Date 4/14/2023

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Document Table of Contents

8.2.1. E-Tile PTP Packet Classifier Registers

All PTP Packet Classifier Registers are 48-bit packet counters. The counter values are represented in 2 registers: lower 32-bit register and upper 16-bit register. Each counter will be frozen when it reaches maximum value and does not roll over. Writing all 1’s value to the lower 32-bit register clears the entire 48-bit counter.