Ethernet Subsystem Intel® FPGA IP User Guide: Early Access Customer Release

Download PDF
ID 773413
Date 4/14/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Introduction 2. Feature Description 3. Ethernet Subsystem Parameters 4. Subsystem Abstraction Layer (SAL) 5. Dynamic Reconfiguration Extension Subsystem 6. Interfaces and Signals 7. Recommended Clock Connections 8. Register Descriptions 9. Ethernet SS IP Example Design 10. Document Revision History for Ethernet Subsystem Intel FPGA IP User Guide: Early Access Customer Release
1. Introduction x
1.1. Supported Features 1.2. Getting Started 1.3. Resource Utilization
2. Feature Description x
2.1. Ethernet Subsystem Intel FPGA IP Overview 2.2. Supported Features
3. Ethernet Subsystem Parameters x
3.1. Parameter Editor Parameters 3.2. E-Tile Port Enablement Guidelines and Restrictions 3.3. F-tile Ethernet Port to PMA Channel Mapping
4. Subsystem Abstraction Layer (SAL) x
4.1. Subsystem Abstraction Layer (SAL) Commands
4.1. Subsystem Abstraction Layer (SAL) Commands x
4.1.1. NOP(0x0) 4.1.2. get_hssi_profile 4.1.3. set_hssi_profile 4.1.4. read_MAC_statistic (0x3) 4.1.5. get_mtu(0x4) 4.1.6. set_csr for E-Tile (0x5) 4.1.7. set_csr for F-Tile 4.1.8. get_csr for E-Tile (0x6) 4.1.9. get_csr for F-Tile 4.1.10. enable_loopback for E-Tile (0x7) 4.1.11. enable_loopback for F-Tile 4.1.12. disable_loopback for E-Tile (0x8) 4.1.13. disable_loopback for F-Tile 4.1.14. Reset MAC Statistics (0x9) 4.1.15. set_mtu for F-Tile 4.1.16. Ncsi_get_link_status 4.1.17. Reserved 4.1.18. firmware_version (0xFF)
6. Interfaces and Signals x
6.1. AXI4 Interfaces 6.2. Serial Interface 6.3. Clocks 6.4. Resets
6.1. AXI4 Interfaces x
6.1.1. AXI-Lite CSR 6.1.2. AXI-ST Client Interface 6.1.3. AXI-ST PHY Direct 6.1.4. AXI-ST PTP 6.1.5. Flow Control
7. Recommended Clock Connections x
7.1. Driving Multiple Ports with the Same Clock 7.2. Alternate Clock Connections for MAC Async Client FIFO 7.3. F-Tile Clock Connections for PTP Synchronous and Asynchronous cases 7.4. Clock Connections for SyncE Operation 7.5. F-Tile PMA and FEC Direct PHY IP Clock Output
8. Register Descriptions x
8.1. Subsystem Registers 8.2. Port Registers 8.3. F-tile Address Maps 8.4. F-tile ANLT Port Register Map 8.5. F-tile PTP Tile Adapter Register Map
8.1. Subsystem Registers x
8.1.1. Device Feature Header Lo 8.1.2. Device Feature Header Hi 8.1.3. Feature GUID_L 8.1.4. Feature GUID_H 8.1.5. Feature CSR ADDR 8.1.6. Feature CSR Size Group 8.1.7. Version 8.1.8. Feature List 8.1.9. Interface Attribute Port X Parameters 8.1.10. HSSI Command/Status 8.1.11. HSSI Control/Address 8.1.12. HSSI Read Data 8.1.13. HSSI Write Data 8.1.14. HSSI Ethernet Port X Status
8.2. Port Registers x
8.2.1. E-Tile PTP Packet Classifier Registers
8.2.1. E-Tile PTP Packet Classifier Registers x
8.2.1.1. Recognized and Unrecognized Packet Counters 8.2.1.2. Parse Graph Specific Packet Counters
9. Ethernet SS IP Example Design x
9.1. Steps to Generate the Example Design 9.2. Supported Simulators 9.3. Running the Simulation Tests 9.4. Running the Hardware Tests
9.3. Running the Simulation Tests x
9.3.1. Steps to Simulate the Design Example
9.4. Running the Hardware Tests x
9.4.1. Supported Boards 9.4.2. Steps to Compile the Design Example for Hardware 9.4.3. Steps to Run the Design Example on Hardware
1. Introduction
2. Feature Description
3. Ethernet Subsystem Parameters
4. Subsystem Abstraction Layer (SAL)
5. Dynamic Reconfiguration Extension Subsystem
6. Interfaces and Signals
7. Recommended Clock Connections
8. Register Descriptions
9. Ethernet SS IP Example Design
10. Document Revision History for Ethernet Subsystem Intel FPGA IP User Guide: Early Access Customer Release

4.1.11. enable_loopback for F-Tile

Issuing the enable_loopback SAL command enables the serial loopback mode on FGT and FHT PMA (port 0 - 19). Below are the CSR sequences carried out by NIOS FW to enable serial loopback for F-tile transceiver PMA.

For FHT PMA (port 16 - 19),

  • Assert rx_reset.
  • Write 1'b1 to 0x45800[14] CSR register bit to enable serial internal loopback.
  • Deassert rx_reset.
  • Set car_tx_clk_src_sel (0x60000[2]) to 1’b1.
  • Set cfg_tx_bus_take_dft (0x45804[0]) to 1’b1. If using multi-lanes, set 1’b1 to all lanes.
  • Set cfg_lane_tx_prbs_en (0x42934[0]) to 1’b1. If using multi-lanes, set 1’b1 to all lanes.
  • Specify the PRBS generator pattern cfg_lane_tx_prbs_mode (0x42934[4:1]). If using multi-lanes, specify for all lanes.
  • Set cfg_lane_tx_prbs_init (0x4293C[0]) to 1’b1. If using multi-lanes, set 1’b1 to all lanes.
  • Set cfg_dft_rx_prbs_common_en (0x42930[0]) to 1’b1. If using multi-lanes, set 1’b1 to all lanes.
  • Specify the PRBS verifier pattern, cfg_dft_rx_prbs_sel (0x42930[4:1]). If using multi-lanes, specify for all lanes.
  • Set cfg_rx_dft_data_sel (0x42930[6:5]) to 2’b00. If using multi-lanes, set 2’b00 to all lanes.
  • Set cfg_ber_symb_cnt_limit_lsb (0x428EC[31:0]). If using multi-lanes, set for all lanes.
  • Set cfg_ber_symb_cnt_limit_msb (0x428F0[31:0]). If using multi-lanes, set for all lanes.
  • Set cfg_dft_ber_count_en (0x428DC[0]) to 1’b1. If using multi-lanes, set 1’b1 to all lanes.
  • Set cfg_dft_ber_count_mode (0x428DC[2:1]) to 2’b10. If using multi-lanes, set 2’b10 to all lanes.
For FGT PMA (port 0 - 15),
  • Assert rx_reset.
  • Enable serial loopback:
    1. Write 0x6A040 to address 0x9003C.
    2. Poll address 0x90040 until bit 14 = 0 and bit 15 = 1.
    3. Write 0x62040 to address 0x9003C.
    4. Poll address 0x90040 until bit 14 = 0 and bit 15 = 0.
  • Deassert rx_reset.
  • Confirm the channel is in serial loopback:
    1. Read out register 0x4781C; bit 1 should be high if serial loopback is enabled.
  • Check the FGT PMA’s status:
    1. Write 0x800D to address 0x9003C.
    2. Poll address 0x90040 until bit 15 = 1; bit 16 should also be high if the channel is located in physical local 0.
    3. Write 0x000D to address 0x9003C.
    4. Poll address 0x90040 until bit 15 = 0.
  • Set the PRBS31 pattern for both the TX and RX PMAs:
    1. Write 0x30CA041 to address 0x9003C.
    2. Poll address 0x90040 until bit 15 = 1.
    3. Write 0x30C2041 to address 0x9003C.
    4. Poll address 0x90040 until bit 15 = 0.
  • Set up the PMA to count the number of bit errors:
    1. Write 0x14A045 to address 0x9003C.
    2. Poll address 0x90040 until bit 15 = 1.
    3. Write 0x14C2045 to address 0x9003C.
    4. Poll address 0x90040 until bit 15 = 0.
    Note: This example selects the PRBS31 pattern for both the TX and RX PMA lanes and hence bits [27:16] for register 0x9003C are set to 0x30C. To select other PRBS patterns, set bits [27:16] for register 0x9003C as follows:
    • PRBS7: 0x208
    • PRBS9: 0x249
    • PRBS11: 0x28A
    • PRBS23: 0x2CB
    • QPRBS13: 0x34D
    • PRBS13Q: 0x820
    • PRBS31Q: 0x861
    • SSPR: 0x8A2
    • SSPR1: 0x8E3
    • SSPRQ: 0x924
    • PRBS13: 0x965
  • Start the test:
    1. Write 0x20A00F to address 0x9003C.
    2. Poll address 0x90040 until bit 15 = 1.
    3. Write 0x20200F to address 0x9003C.
    4. Poll address 0x90040 until bit 15 = 0.
  • Check that the test is running:
    1. Write 0x8049 to address 0x9003C.
    2. Poll address 0x90040 until bit 15 = 1; bits 25:24 should be 0x1 to indicate the test is running.
    3. Write 0x0049 to address 0x9003C.
    4. Poll address 0x90040 until bit 15 = 0.
  • Set up the PRBS generator to inject errors:
    1. Write 0x123A042 to address 0x9003C to inject 0x123 errors.
    2. Poll address 0x90040 until bit 15 = 1.
    3. Write 0x1232042 to address 0x9003C.
    4. Poll address 0x90040 until bit 15 = 0.
  • Tell the PRBS generator to inject errors:
    1. Write 0x23A00F to address 0x9003C.
    2. Poll address 0x90040 until bit 15 = 1.
    3. Write 0x23200F to address 0x9003C.
    4. Poll address 0x90040 until bit 15 = 0.
  • Stop the BER test:
    1. Write 0x21A00F to address 0x9003C.
    2. Poll address 0x90040 until bit 15 = 1.
    3. Write 0x21200F to address 0x9003C.
    4. Poll address 0x90040 until bit 15 = 0.
  • Check the test completed successfully:
    1. Write 0x8049 to address 0x9003C.
    2. Poll address 0x90040 until bit 15 = 1; bits 25:24 should be 0x3.
    3. Write 0x0049 to address 0x9003C.
    4. Poll address 0x90040 until bit 15 = 0.
  • Read out the 12 LSB of the error count:
    1. Write 0x804A to address 0x9003C.
    2. Poll address 0x90040 until bit 15 = 1; bits 27:16 represent the 12 LSBs of the error count.
    3. Write 0x004A to address 0x9003C.
    4. Poll address 0x90040 until bit 15 = 0.
  • Read out bits 27:12 of the error count:
    1. Write 0x804B to address 0x9003C.
    2. Poll address 0x90040 until bit 15 = 1; bits 31:16 represent bits 27:12 of the error count.
    3. Write 0x004B to address 0x9003C.
    4. Poll address 0x90040 until bit 15 = 0.
  • Read out bits 31:28 of the error count:
    1. Write 0x804C to address 0x9003C.
    2. Poll address 0x90040 until bit 15 = 1; bits 19:16 represent bits 31:28 of the error count.
    3. Write 0x004C to address 0x9003C.
    4. Poll address 0x90040 until bit 15 = 0.
  • Finish checking the PRBS and BER test:
    1. Write 0xA041 to address 0x9003C.
    2. Poll address 0x90040 until bit 15 = 1.
    3. Write 0x2041 to address 0x9003C.
    4. Poll address 0x90040 until bit 15 = 0.
Level Two Title