Ethernet Subsystem Intel® FPGA IP User Guide: Early Access Customer Release

ID 773413
Date 4/14/2023
Public

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6.1.4. AXI-ST PTP

The AXI-ST PTP Interface is available when PTP feature is enabled for the user selected subsystem Profile.
Table 21.  AXI-ST Tx ToD Interface Signals
Signal Name Direction Type Description
p<n>_app_ss_st_txtod_tvalid In Control Data valid signal.
p<n>_app_ss_st_txtod_tdata[95:0] In Data

Time-of Day according to the Local Clock for TX data path.

This bus is used to present the current time of day (according to the local clock) to the TX data path of the Ethernet core.

The format of the time is IEEE 1588v2 (96 bits).

[95:48]:Seconds

[47:16]:Nanoseconds

[15:0]:Fractional nanoseconds

Table 22.  AXI-Rx ToD Interface Signals
Signal Name Direction Type Description
p<n>_app_ss_st_rxtod_tvalid In Control Datavalid signal.
p<n>_app_ss_st_rxtod_tdata[95:0] In Data

Time-of Day according to the Local Clock for the TX data path.

This bus is used to present the current time of day (according to the local clock) to the TX data path of Ethernet Core.

The format of the time is IEEE 1588v2 (96 bits)

[95:48]:Seconds

[47:16]:Nanoseconds

[15:0]:Fractional nanoseconds.

Table 23.  AXI-ST Tx Egress Timestamp 0 Interface Signals
Signal Name Direction Type Description
p<n>_ss_app_st_txegrts0_tvalid Out Control TXEgress Timestamp valid signal.
p<n>_ss_app_st_txegrts0_tdata[103:0] Out Data

bits [103:96] - o_ptp_ets_fp[7:0]:TX Egress Timestamp Fingerprint.

bits [95:0] - o_ptp_ets[95:0]:TXEgress Timestamp.

[95:48]:Seconds.

[47:16]:Nanoseconds.

[15:0]:Fractional nanoseconds.

Table 24.  AXI-ST Tx Egress Timestamp 1 Interface SignalsThe AXI-ST Tx Egress Timestamp 1 Interface Signals only exist on F-tile.
Signal Name Direction Type Description
p{0..15}_ss_app_st_txegrts1_tvalid Out Control

Valid. Asserted when internal signal o_ptp_ets_valid[1:1] asserted.

o_ptp_ets_valid[1:1] - TX Egress Timestamp Valid when rate is 400G

p{0..15}_ss_app_st_txegrts1_tdata Out Data

Data.

[<w>+96:96] - o_ptp_ets_fp[<w>*2-1:w] (TX Egress Timestamp Fingerprint when rate is 400G)

[95:0] - o_ptp_ets[191:96] (TX Egress Timestamp when rate is 400G)

* w is set to 8 by default. If w is configured to more than 8 (maximum 32 in F-tile, 8 in E-tile)

Table 25.  AXI-ST Rx Ingress Timestamp 0 Interface Signals
Signal Name Direction Type Description
p<n>_ss_app_st_rxingrts0_tvalid Out Control RXingress Timestamp valid signal.
p<n>_ss_app_st_rxingrts0_tdata[95:0]

Out

Data

o_ptp_rx_its[95:0]:

Ingress RX timestamp signal.

[95:48]:Seconds

[47:16]:Nanoseconds

[15:0]:Fractional nanoseconds

Table 26.  AXI-ST Rx Ingress Timestamp 1 Interface SignalsThe AXI-ST Rx Ingress Timestamp 1 Interface Signals only exist on F-tile.
Signal Name Direction Type Description
p{0..15}_ss_app_st_rxingrts1_tvalid Out Control

Valid. Asserted when internal signal o_ptp_rx_its_valid [1:1] asserted.

o_ptp_rx_its_valid[1:1] - RX Ingress Timestamp Valid when rate is 400G

p{0..15}_ss_app_st_rxingrts1_tdata [95:0] Out Data

Data.

[95:0] - o_ptp_rx_its[181:96] (TR Egress Timestamp when rate is 400G