Ethernet Subsystem Intel® FPGA IP User Guide: Early Access Customer Release
ID
773413
Date
4/14/2023
Public
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1. Introduction
2. Feature Description
3. Ethernet Subsystem Parameters
4. Subsystem Abstraction Layer (SAL)
5. Dynamic Reconfiguration Extension Subsystem
6. Interfaces and Signals
7. Recommended Clock Connections
8. Register Descriptions
9. Ethernet SS IP Example Design
10. Document Revision History for Ethernet Subsystem Intel FPGA IP User Guide: Early Access Customer Release
4.1.1. NOP(0x0)
4.1.2. get_hssi_profile
4.1.3. set_hssi_profile
4.1.4. read_MAC_statistic (0x3)
4.1.5. get_mtu(0x4)
4.1.6. set_csr for E-Tile (0x5)
4.1.7. set_csr for F-Tile
4.1.8. get_csr for E-Tile (0x6)
4.1.9. get_csr for F-Tile
4.1.10. enable_loopback for E-Tile (0x7)
4.1.11. enable_loopback for F-Tile
4.1.12. disable_loopback for E-Tile (0x8)
4.1.13. disable_loopback for F-Tile
4.1.14. Reset MAC Statistics (0x9)
4.1.15. set_mtu for F-Tile
4.1.16. Ncsi_get_link_status
4.1.17. Reserved
4.1.18. firmware_version (0xFF)
8.1.1. Device Feature Header Lo
8.1.2. Device Feature Header Hi
8.1.3. Feature GUID_L
8.1.4. Feature GUID_H
8.1.5. Feature CSR ADDR
8.1.6. Feature CSR Size Group
8.1.7. Version
8.1.8. Feature List
8.1.9. Interface Attribute Port X Parameters
8.1.10. HSSI Command/Status
8.1.11. HSSI Control/Address
8.1.12. HSSI Read Data
8.1.13. HSSI Write Data
8.1.14. HSSI Ethernet Port X Status
4.1. Subsystem Abstraction Layer (SAL) Commands
Section Content
NOP(0x0)
get_hssi_profile
set_hssi_profile
read_MAC_statistic (0x3)
get_mtu(0x4)
set_csr for E-Tile (0x5)
set_csr for F-Tile
get_csr for E-Tile (0x6)
get_csr for F-Tile
enable_loopback for E-Tile (0x7)
enable_loopback for F-Tile
disable_loopback for E-Tile (0x8)
disable_loopback for F-Tile
Reset MAC Statistics (0x9)
set_mtu for F-Tile
Ncsi_get_link_status
Reserved
firmware_version (0xFF)