Ethernet Subsystem Intel® FPGA IP User Guide: Early Access Customer Release

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ID 773413
Date 4/14/2023
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Feature Description 3. Ethernet Subsystem Parameters 4. Subsystem Abstraction Layer (SAL) 5. Dynamic Reconfiguration Extension Subsystem 6. Interfaces and Signals 7. Recommended Clock Connections 8. Register Descriptions 9. Ethernet SS IP Example Design 10. Document Revision History for Ethernet Subsystem Intel FPGA IP User Guide: Early Access Customer Release
1. Introduction x
1.1. Supported Features 1.2. Getting Started 1.3. Resource Utilization
2. Feature Description x
2.1. Ethernet Subsystem Intel FPGA IP Overview 2.2. Supported Features
3. Ethernet Subsystem Parameters x
3.1. Parameter Editor Parameters 3.2. E-Tile Port Enablement Guidelines and Restrictions 3.3. F-tile Ethernet Port to PMA Channel Mapping
4. Subsystem Abstraction Layer (SAL) x
4.1. Subsystem Abstraction Layer (SAL) Commands
4.1. Subsystem Abstraction Layer (SAL) Commands x
4.1.1. NOP(0x0) 4.1.2. get_hssi_profile 4.1.3. set_hssi_profile 4.1.4. read_MAC_statistic (0x3) 4.1.5. get_mtu(0x4) 4.1.6. set_csr for E-Tile (0x5) 4.1.7. set_csr for F-Tile 4.1.8. get_csr for E-Tile (0x6) 4.1.9. get_csr for F-Tile 4.1.10. enable_loopback for E-Tile (0x7) 4.1.11. enable_loopback for F-Tile 4.1.12. disable_loopback for E-Tile (0x8) 4.1.13. disable_loopback for F-Tile 4.1.14. Reset MAC Statistics (0x9) 4.1.15. set_mtu for F-Tile 4.1.16. Ncsi_get_link_status 4.1.17. Reserved 4.1.18. firmware_version (0xFF)
6. Interfaces and Signals x
6.1. AXI4 Interfaces 6.2. Serial Interface 6.3. Clocks 6.4. Resets
6.1. AXI4 Interfaces x
6.1.1. AXI-Lite CSR 6.1.2. AXI-ST Client Interface 6.1.3. AXI-ST PHY Direct 6.1.4. AXI-ST PTP 6.1.5. Flow Control
7. Recommended Clock Connections x
7.1. Driving Multiple Ports with the Same Clock 7.2. Alternate Clock Connections for MAC Async Client FIFO 7.3. F-Tile Clock Connections for PTP Synchronous and Asynchronous cases 7.4. Clock Connections for SyncE Operation 7.5. F-Tile PMA and FEC Direct PHY IP Clock Output
8. Register Descriptions x
8.1. Subsystem Registers 8.2. Port Registers 8.3. F-tile Address Maps 8.4. F-tile ANLT Port Register Map 8.5. F-tile PTP Tile Adapter Register Map
8.1. Subsystem Registers x
8.1.1. Device Feature Header Lo 8.1.2. Device Feature Header Hi 8.1.3. Feature GUID_L 8.1.4. Feature GUID_H 8.1.5. Feature CSR ADDR 8.1.6. Feature CSR Size Group 8.1.7. Version 8.1.8. Feature List 8.1.9. Interface Attribute Port X Parameters 8.1.10. HSSI Command/Status 8.1.11. HSSI Control/Address 8.1.12. HSSI Read Data 8.1.13. HSSI Write Data 8.1.14. HSSI Ethernet Port X Status
8.2. Port Registers x
8.2.1. E-Tile PTP Packet Classifier Registers
8.2.1. E-Tile PTP Packet Classifier Registers x
8.2.1.1. Recognized and Unrecognized Packet Counters 8.2.1.2. Parse Graph Specific Packet Counters
9. Ethernet SS IP Example Design x
9.1. Steps to Generate the Example Design 9.2. Supported Simulators 9.3. Running the Simulation Tests 9.4. Running the Hardware Tests
9.3. Running the Simulation Tests x
9.3.1. Steps to Simulate the Design Example
9.4. Running the Hardware Tests x
9.4.1. Supported Boards 9.4.2. Steps to Compile the Design Example for Hardware 9.4.3. Steps to Run the Design Example on Hardware
1. Introduction
2. Feature Description
3. Ethernet Subsystem Parameters
4. Subsystem Abstraction Layer (SAL)
5. Dynamic Reconfiguration Extension Subsystem
6. Interfaces and Signals
7. Recommended Clock Connections
8. Register Descriptions
9. Ethernet SS IP Example Design
10. Document Revision History for Ethernet Subsystem Intel FPGA IP User Guide: Early Access Customer Release

4.1.4. read_MAC_statistic (0x3)

Table 14.   read_MAC_statistic (0x3) The following table above shows the statistic counters of Ethernet Subsystem and the mapping to internal Ethernet IP statistic registers.
Ethtool Statistics HSSI Control/Address bit[20:16] Counters E-tile Hard IP for Ethernet Statistics Registers
tx_packets 0 TX_MCAST_DATA_OK_31_0 + TX_MCAST_DATA_OK_63_32+ TX_BCAST_DATA_OK_31_0 + TX_BCAST_DATA_OK_63_32 + TX_UCAST_DATA_OK_31_0 + TX_UCAST_DATA_OK_63_32 + TX_MCAST_CTRL_OK_31_0 + TX_MCAST_CTRL_OK_63_32 + TX_BCAST_CTRL_OK_31_0 + TX_BCAST_CTRL_OK_63_32 + TX_UCAST_CTRL_OK_31_0 + TX_UCAST_CTRL_OK_63_32
rx_packets 1 RX_MCAST_DATA_OK_31_0 + RX_MCAST_DATA_OK_63_32+ RX_BCAST_DATA_OK_31_0 + RX_BCAST_DATA_OK_63_32 + RX_UCAST_DATA_OK_31_0 + RX_UCAST_DATA_OK_63_32 + RX_MCAST_CTRL_OK_31_0 + RX_MCAST_CTRL_OK_63_32 + RX_BCAST_CTRL_OK_31_0 + RX_BCAST_CTRL_OK_63_32 + RX_UCAST_CTRL_OK_31_0 + RX_UCAST_CTRL_OK_63_32
rx_crc_errors 2 RX_FCSERR_31_0+ RX_FCSERR_63_32
rx_align_errors 3 RX_FCSERR_31_0+ RX_FCSERR_63_32 - (RX_RNT_31_0 + RX_RNT_63_32)
tx_bytes 4 TX_Payload_OctetsOK_31_0+ TX_Payload_OctetsOK_63_32
rx_bytes 5 RX_Payload_OctetsOK_31_0+ RX_Payload_OctetsOK_63_32
tx_pause 6 TX_PAUSE_31_0+ TX_PAUSE_63_32
rx_pause 7 RX_PAUSE_31_0+ RX_PAUSE_63_32
rx_errors 8 RX_Dropped_CTRL_31_0+ RX_Dropped_CTRL_63_32
tx_errors 9 TX_Dropped_CTRL_31_0+ TX_Dropped_CTRL_63_32
rx_unicast 10 RX_UCAST_DATA_OK_31_0 + RX_UCAST_DATA_OK_63_32+ RX_UCAST_CTRL_OK_31_0 + RX_UCAST_CTRL_OK_63_32
rx_multicast 11 RX_MCAST_DATA_OK_31_0 + RX_MCAST_DATA_OK_63_32+ RX_MCAST_CTRL_OK_31_0 + RX_MCAST_CTRL_OK_63_32
rx_broadcast 12 RX_BCAST_DATA_OK_31_0 + RX_BCAST_DATA_OK_63_32+ RX_BCAST_CTRL_OK_31_0 + RX_BCAST_CTRL_OK_63_32
tx_discards 13 -
tx_unicast 14 TX_UCAST_DATA_OK_31_0 + TX_UCAST_DATA_OK_63_32+ TX_UCAST_CTRL_OK_31_0 + TX_UCAST_CTRL_OK_63_32
tx_multicast 15 TX_MCAST_DATA_OK_31_0 + TX_MCAST_DATA_OK_63_32+ TX_MCAST_CTRL_OK_31_0 + TX_MCAST_CTRL_OK_63_32
tx_broadcast 16 TX_BCAST_DATA_OK_31_0 + TX_BCAST_DATA_OK_63_32+ TX_BCAST_CTRL_OK_31_0 + TX_BCAST_CTRL_OK_63_32
ether_drops 17 RX_Dropped_CTRL_31_0+ RX_Dropped_CTRL_63_32
rx_total_bytes 18 RX_Frame_OctetsOK_31_0+ RX_Frame_OctetsOK_63_32
rx_total_packets 19 TX_MCAST_DATA_OK_31_0 + TX_MCAST_DATA_OK_63_32 + TX_BCAST_DATA_OK_31_0 + TX_BCAST_DATA_OK_63_32 + TX_UCAST_DATA_OK_31_0 + TX_UCAST_DATA_OK_63_32 + TX_MCAST_CTRL_OK_31_0 + TX_MCAST_CTRL_OK_63_32 + TX_BCAST_CTRL_OK_31_0 + TX_BCAST_CTRL_OK_63_32 + TX_UCAST_CTRL_OK_31_0 + TX_UCAST_CTRL_OK_63_32 + RX_MCAST_DATA_ERR_31_0 + RX_MCAST_DATA_ERR_63_32+ RX_BCAST_DATA_ERR_31_0 + RX_BCAST_DATA_ERR_63_32 + RX_UCAST_DATA_ERR_31_0 + RX_UCAST_DATA_ERR_63_32 + RX_MCAST_CTRL_ERR_31_0 + RX_MCAST_CTRL_ERR_63_32 + RX_BCAST_CTRL_ERR_31_0 + RX_BCAST_CTRL_ERR_63_32 + RX_UCAST_CTRL_ERR_31_0 + RX_UCAST_CTRL_ERR_63_32
rx_undersize 20 RX_RNT_31_0+ RX_RNT_63_32
rx_oversize 21 RX_OVERSIZE_31_0+ RX_OVERSIZE_63_32
rx_64_bytes 22 RX_64B_31_0+ RX_64B_63_32
rx_65_127_bytes 23 RX_65to127B_31_0+ RX_65to127B_63_32
rx_128_255_bytes 24 RX_128to255B_31_0+ RX_128to255B_63_32
rx_256_511_bytes 25 RX_256to511B_31_0+ RX_256to511B_63_32
rx_512_1023_bytes 26 RX_512to1023B_31_0+ RX_512to1023B_63_32
rx_1024_1518_bytes 27 RX_1024to1518B_31_0+ RX_1024to1518B_63_32
rx_gte_1519_bytes 28 RX_1519toMAXB_31_0+ RX_1519toMAXB_63_32
rx_jabbers 29 RX_JABBERS_31_0+ RX_JABBERS_63_32
rx_runts 30 RX_ FRAGMENTS _31_0+ RX_ FRAGMENTS _63_32

User should write to HSSI Control/Address Register bit [20:16] to identify which counter to be read out based on the counter value from the above table. The result is calculated by aggregating internal statistic register values read out from Ethernet IP. The HSSI Control/Address Register bit 31 indicates the read is intended for lower 32 bits (1'b1) of the statistic counters or the upper 32 bits (1'b0).

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