Ethernet Subsystem Intel® FPGA IP User Guide: Early Access Customer Release

ID 773413
Date 4/14/2023

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4.1.6. set_csr for E-Tile (0x5)

set_csr SAL command is an indirect CSR access to write to registers of the Ethernet Subsystem. The CSR address and write data are written into the HSSI Control/Address Register and the Write Data Register respectively. Then, a write to the HSSI Command/Status CSR is required to trigger the write CSR operation.

For base addresses, refer to Register Descriptions.

For register map of E-tile Hard IP for Ethernet Hard IP, refer to Port Registers.

You need to multiply the register address in word offset by four then add the base address of the channel to obtain the CSR address on that channel. If the CSR address is in byte offset (for example PTP registers), the offset is directly added to base address without multiplication. To access these registers, the software will write bit [25:2] of the calculated address to HSSI Control/Address Register with set_csr SAL command.

Example on accessing Subsystem IP register:

To access TX MAC Link Fault Configuration register of Port 4:

TX MAC Link Fault Configuration register word offset = 0x405

Base address of Port 4 = 0x120_0000

AXI-Lite CSR read request address = 0x405*4 + 0x120_0000 = 0x120_1014 (byte addressing)

Write bit [25:2] of the calculated address to HSSI Control/Address Register Address field = 0x120_1014 / 4 = 0x48_0405

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