Ethernet Subsystem Intel® FPGA IP User Guide: Early Access Customer Release

ID 773413
Date 4/14/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

7.5. F-Tile PMA and FEC Direct PHY IP Clock Output

The Ethernet SS supports six different clock output options from TX and RX that you can use for FPGA core clocking.

Refer to Clocking in F-Tile Architecture and PMA and FEC Direct PHY IP User Guide.