Ethernet Subsystem Intel® FPGA IP User Guide: Early Access Customer Release

ID 773413
Date 4/14/2023

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7.3. F-Tile Clock Connections for PTP Synchronous and Asynchronous cases

The following figure the clocking for each Ethernet port when PTP is enabled.
Figure 11. Clock Connections for PTP Synchronous and Asynchronous Cases

When Enable IEEE 1588 PTP is selected, all ports must be clocked by system clock source o_p<n>_clk_pll of PTP Tile Adapter. System clk/2 at minimum 402.83 MHz is required.

When PTP and asynchronous adapter option are enabled, i_clk_pll is connected to the same system clock source.

PTP Tile Adapter i_sys_clk is also sourced from its own o_p<n>_clk_pll.