7.3. F-Tile Clock Connections for PTP Synchronous and Asynchronous cases
When Enable IEEE 1588 PTP is selected, all ports must be clocked by system clock source o_p<n>_clk_pll of PTP Tile Adapter. System clk/2 at minimum 402.83 MHz is required.
When PTP and asynchronous adapter option are enabled, i_clk_pll is connected to the same system clock source.
PTP Tile Adapter i_sys_clk is also sourced from its own o_p<n>_clk_pll.