Ethernet Subsystem Intel® FPGA IP User Guide: Early Access Customer Release

ID 773413
Date 4/14/2023

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5. Dynamic Reconfiguration Extension Subsystem

The following diagram shows the Dynamic Reconfiguration (DR) Extension Subsystem when it is enabled in the Subsystem GUI. The Subsystem Abstraction Layer (SAL) is always included as part of the Ethernet Subsystem, including the HSSI control and status registers.
Figure 6. Dynamic Reconfiguration Extension Subsystem

The main functionality of the DR Extension Subsystem is to provide a standard mechanism for external software to allow you to dynamically reconfigure a subset of the transceiver channels to operate in different modes (e.g.: data rates) without impacting the adjacent active channels.

The Host CPU communicates with the NIOS soft microcontroller via four 32 bits registers, HSSI Command/Status, HSSI Control/Address, HSSI Write Data, and HSSI Read Data CSRs. The control registers are 32 bits read/write which travel from the external host software to the NIOS. The detail of HSSI Control and Status 0/1 usage are covered in Subsystem Abstraction Layer section.

The external software can make simple “peek/poke” style transaction requests to the NIOS using a traditional asynchronous handshake procedure. You must be aware that the NIOS is not optimized for speed. It is expected to take a few microseconds to complete and acknowledge most transactions.

The internal DR handshake procedure is slightly different between Agilex E/F-tile. In F-tile, the DR triggering is performed by the host through writing into DR SIP CSR which is located at base address 0x200 - 0x27F in Subsystem CSR register space.