Ethernet Subsystem Intel® FPGA IP User Guide: Early Access Customer Release

ID 773413
Date 4/14/2023

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4.1.9. get_csr for F-Tile

get_csr SAL command is an indirect CSR access to read to HSSI SS CSRs. The CSR address and is written into HSSI Address CSR respectively and then write to HSSI Command/Status CSR to trigger the read CSR operation. The CSR read data is written into HSSI Read Data CSR.

ROffset field in HSSI Command/Status Register is not used and not applicable for F-tile since both Ethernet Reconfiguration Avalon® Mapped-memory and Transceiver Reconfiguration Avalon® Mapped-memory supports 32b access with byte enable.

Refer to set_csr for F-Tile example above to determine the Address[25:2] field in the HSSI Control/Address CS.

RSFEC registers read is per 32 bits,

  • Write HSSI Control/Address Register 0x6 (SAL get_csr Command), 0x0 (Port), 0x0 (Channel), Address[25:2] (RSFEC registers address)
  • Write HSSI Command/Status Register to configure READ_CMD = 1, WRITE_CMD = 0, ROffset = 0 (ignored)
    • Subsystem internally generate single RSFEC register read
  • Read HSSI Command/Status Register ACK_TRANS, BUSY and ERROR
  • If ACK_TRANS = 1 and BUSY/ERROR = 0
  • Read HSSI Read Data [7:0] for RSFEC register data
  • Write 0x0 to clear HSSI Command/Status and HSSI Control/Address