Ethernet Subsystem Intel® FPGA IP User Guide: Early Access Customer Release

ID 773413
Date 4/14/2023

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7.1. Driving Multiple Ports with the Same Clock

The figure in Recommended Clock Connections for Normal Operation in Recommended Clock Connections is simple and functions correctly, however, it is better to share a single clock between multiple ports.

Figure 9. Sharing o_p<n>_clk_pll

It is possible to share the same clock source between multiple Ethernet ports as long as the following conditions are met:

  • The shared clock can be traced to a common source reference clock. You must note that any clock source that derives the correct clock frequency from the same source clock as the port’s i_ref_clk can be used to drive the datapath clocks. Here are a few examples of alternative clock sources.
    • o_p<n>_clk_pll or its equivalent from an unrelated transceiver tile that is connected to the same reference clock source, and whose system clock is configured to the same rate (For F-tile).
    • An IO PLL or FPLL in fabric that derives its refclk from the same reference clock source.
    • A GPIO directly connected to the reference clock, providing a 161.1328125 MHz clock to a port that can use p<n>_app_ss_st_tx_clk/p<n>_app_ss_st_rx_clk running at that speed.

The Tile Refclk/PLL IP and i_clk_sys are instantiated within HSSI SS and only applicable for F-tile.