Ethernet Subsystem Intel® FPGA IP User Guide: Early Access Customer Release

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ID 773413
Date 4/14/2023
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Feature Description 3. Ethernet Subsystem Parameters 4. Subsystem Abstraction Layer (SAL) 5. Dynamic Reconfiguration Extension Subsystem 6. Interfaces and Signals 7. Recommended Clock Connections 8. Register Descriptions 9. Ethernet SS IP Example Design 10. Document Revision History for Ethernet Subsystem Intel FPGA IP User Guide: Early Access Customer Release
1. Introduction x
1.1. Supported Features 1.2. Getting Started 1.3. Resource Utilization
2. Feature Description x
2.1. Ethernet Subsystem Intel FPGA IP Overview 2.2. Supported Features
3. Ethernet Subsystem Parameters x
3.1. Parameter Editor Parameters 3.2. E-Tile Port Enablement Guidelines and Restrictions 3.3. F-tile Ethernet Port to PMA Channel Mapping
4. Subsystem Abstraction Layer (SAL) x
4.1. Subsystem Abstraction Layer (SAL) Commands
4.1. Subsystem Abstraction Layer (SAL) Commands x
4.1.1. NOP(0x0) 4.1.2. get_hssi_profile 4.1.3. set_hssi_profile 4.1.4. read_MAC_statistic (0x3) 4.1.5. get_mtu(0x4) 4.1.6. set_csr for E-Tile (0x5) 4.1.7. set_csr for F-Tile 4.1.8. get_csr for E-Tile (0x6) 4.1.9. get_csr for F-Tile 4.1.10. enable_loopback for E-Tile (0x7) 4.1.11. enable_loopback for F-Tile 4.1.12. disable_loopback for E-Tile (0x8) 4.1.13. disable_loopback for F-Tile 4.1.14. Reset MAC Statistics (0x9) 4.1.15. set_mtu for F-Tile 4.1.16. Ncsi_get_link_status 4.1.17. Reserved 4.1.18. firmware_version (0xFF)
6. Interfaces and Signals x
6.1. AXI4 Interfaces 6.2. Serial Interface 6.3. Clocks 6.4. Resets
6.1. AXI4 Interfaces x
6.1.1. AXI-Lite CSR 6.1.2. AXI-ST Client Interface 6.1.3. AXI-ST PHY Direct 6.1.4. AXI-ST PTP 6.1.5. Flow Control
7. Recommended Clock Connections x
7.1. Driving Multiple Ports with the Same Clock 7.2. Alternate Clock Connections for MAC Async Client FIFO 7.3. F-Tile Clock Connections for PTP Synchronous and Asynchronous cases 7.4. Clock Connections for SyncE Operation 7.5. F-Tile PMA and FEC Direct PHY IP Clock Output
8. Register Descriptions x
8.1. Subsystem Registers 8.2. Port Registers 8.3. F-tile Address Maps 8.4. F-tile ANLT Port Register Map 8.5. F-tile PTP Tile Adapter Register Map
8.1. Subsystem Registers x
8.1.1. Device Feature Header Lo 8.1.2. Device Feature Header Hi 8.1.3. Feature GUID_L 8.1.4. Feature GUID_H 8.1.5. Feature CSR ADDR 8.1.6. Feature CSR Size Group 8.1.7. Version 8.1.8. Feature List 8.1.9. Interface Attribute Port X Parameters 8.1.10. HSSI Command/Status 8.1.11. HSSI Control/Address 8.1.12. HSSI Read Data 8.1.13. HSSI Write Data 8.1.14. HSSI Ethernet Port X Status
8.2. Port Registers x
8.2.1. E-Tile PTP Packet Classifier Registers
8.2.1. E-Tile PTP Packet Classifier Registers x
8.2.1.1. Recognized and Unrecognized Packet Counters 8.2.1.2. Parse Graph Specific Packet Counters
9. Ethernet SS IP Example Design x
9.1. Steps to Generate the Example Design 9.2. Supported Simulators 9.3. Running the Simulation Tests 9.4. Running the Hardware Tests
9.3. Running the Simulation Tests x
9.3.1. Steps to Simulate the Design Example
9.4. Running the Hardware Tests x
9.4.1. Supported Boards 9.4.2. Steps to Compile the Design Example for Hardware 9.4.3. Steps to Run the Design Example on Hardware
1. Introduction
2. Feature Description
3. Ethernet Subsystem Parameters
4. Subsystem Abstraction Layer (SAL)
5. Dynamic Reconfiguration Extension Subsystem
6. Interfaces and Signals
7. Recommended Clock Connections
8. Register Descriptions
9. Ethernet SS IP Example Design
10. Document Revision History for Ethernet Subsystem Intel FPGA IP User Guide: Early Access Customer Release

8.1.9. Interface Attribute Port X Parameters

Description: Interface Attribute Port X Parameters, X = 0 - 19 (Depends on NUM_ENABLED_PORTS parameter, read returns reserved value 0 if port does not exist)

E-tile byte offset: 0x68 + X *4

F-tile Byte Offset: 0x300 + X * 4

Addressing Mode: 32 bit

Bit Type Reset Description
31:24 RO 0 Reserved
23:23 RO 0 PTP Enabled
22:22 RO 0 ANLT Enabled
21:21 RO 0 RSFEC Enabled
20:16 RO 0

Port X Sub-Profiles.

5'b10000 and above - Reserved

5'b01111 - 24G PCS

5'b01110 - 12G PCS

5'b01101 - 10G PCS

5'b01100 - 9.8G PMA

5'b01011 - 8.1G PMA

5'b01010 - 6.1G PMA

5'b01001 - 4.9G PMA

5'b01000 - 3.0G PMA

5'b00111 - 2.4G PMA

5'b00110 - 1.2G PMA

5'b00101 - 0.6G PMA

5'b00100 - MAC + PCS

5'b00011 - PCS

5'b00010 - FlexE

5'b00001 - OTN

5'b00000 - None
15:15 RO 0

Indicate presence of Dynamic Reconfiguration in Partial Reconfiguration use case.

1 - Dynamic Reconfiguration in Partial Reconfiguration use case present

0 - Dynamic Reconfiguration in Partial Reconfiguration use case not present
14:13 RO 0

Low Speed Ethernet MAC Interface (PORTX_LOW_SPEED_ETH parameter).

2'b10: XGMII

2'b01: GMII

2'b00: MII
12:10 RO 0

Port X Data Bus Width (PORTX_DATA_WIDTH parameter).

3'b101: 1024

3'b100: 512

3'b011: 256 (Client) / 320 (PHY Direct, 100G)

3'b010: 128

3'b001: 64 (Client) / 80 (PHY Direct, 25G)

3'b000: 32
9:6 RO 0 Port X Ready Latency (PORTX_READY_LATENCY parameter).
5:0 RO 0

Port X Profiles (PORTX_PROFILE).

6'b100001: CPRI,

6'b100000: 400GAUI-8,

6'b011111: 400GAUI-4,

6'b011110: 200GAUI-8,

6'b011101: 200GAUI-4,

6'b011100: 200GAUI-2,

6'b011011: 100GCAUI-4,

6'b011010: 100GAUI-2,

6'b011001: 100GAUI-1,

6'b011000: 50GAUI-1,

6'b010111: 50GAUI-2,

6'b010110: 40GCAUI-4,

6'b010101: 25GbE,

6'b010100: 10GbE,

6'b010011: Ethernet PMA-Direct,

6'b010010: Ethernet FEC-Direct,

6'b010001: Ethernet PCS-Direct,

6'b010000: MII,

6'b001111: General PMA-Direct,

6'b001110: General FEC-Direct,

6'b001101: General PCS-Direct,

6'b001100: OTN,

6'b001011: Flex-E,

6'b001010: TSE MAC,

6'b001001: TSE PCS,

6'b001000: LL10G,

6'b000111: MRPHY,

6'b000110: 10_25G,

6'b000101: 25_50G,

6'b000100: Ultra40G,

6'b000011: LL40G,

6'b000010: LL50G,

6'b000001: Ultra100G,

6'b000000: LL100G,
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