Ethernet Subsystem Intel® FPGA IP User Guide: Early Access Customer Release

ID 773413
Date 4/14/2023

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Document Table of Contents

2.1. Ethernet Subsystem Intel FPGA IP Overview

The figure below displays the Subsystem IP block diagram, showing important blocks and their connections. The same implementation applies to all supported data rate IP options.
Figure 1. Ethernet Subsystem Intel FPGA IP Block Diagram

With MAC and PCS sub-profile, Ethernet frames can be transmitted from the client interface and received from Subsystem IP through AXI4-Streaming interface. Each enabled port will have individual AXI-ST interface. The AXI4 Streaming – AVST bridge converts this interface to Avalon® -Streaming protocol and interfaces with Avalon-Streaming client interface of E-tile Hard IP for Ethernet.

AXI4-Lite Fabric Register Access block translates register access requests from AXI4-Lite client interface to Avalon® memory-mapped interface. This module also decodes incoming requests based on the address and routes them to subsystem registers and reconfiguration interfaces of respective ports.

IEEE 1588 PTP timestamping requires an external time-of-day (TOD) modules to Subsystem IP via PTP interface to provide continuous flow of current timeof-day information. On E-tile, if Enable Tx PTP Packet Classifier is selected, a TX PTP Packet Classifier will be instantiated. This module decodes incoming PTP packets and generate required PTP sideband signals to E-tile Hard IP.