Ethernet Subsystem Intel® FPGA IP User Guide: Early Access Customer Release

ID 773413
Date 4/14/2023

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7.4. Clock Connections for SyncE Operation

The following figure shows an alternate clocking arrangement for the transceiver reference clock that can be used to enable SyncE operation.
Figure 12. Alternate Clock Connections for SyncE Operation

From the figure, it is important to note:

  • Two or more ports can share the clock output of an Off-chip Cleanup PLL that meets the specification for a SyncE link.
  • The FPGA provides a Primary SyncE clock and a backup SyncE clock to the cleanup PLL.
  • The Primary and backup cleanup clocks come from recovered clock output pins from a pair of ports that are both connected to remote stations connected to the same SyncE network, with the transceiver reference clock sourced from the output of the cleanup PLL.
  • In the above figure, o_p<n>_clk_rec_div64 is used; o_p<n>_clk_rec_div can also be used.
  • You must note if the EHIP System clock is derived from a different reference clock than the transceiver, then the IP must be set to Custom Cadence mode to match the PPM difference between the clocks.
  • SyncE clocking can be combined with the datapath clocking schemes shown in the previous sections.
Note: The Ethernet ports do not have to be part of the same instance of the core, or variant.