Ethernet Subsystem Intel® FPGA IP User Guide: Early Access Customer Release

ID 773413
Date 4/14/2023

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4.1.15. set_mtu for F-Tile

Issuing set_mtu SAL command triggers 2 CSR write operations to write to Maximum TX Size Config CSR (offset 0x1208) value and Maximum RX Size Config CSR (offset 0x121C). The HSSI Write Data CSR is written with 16 bits of Maximum TX Frame Size to the LSB and 16 bits of Maximum RX Frame Size to the MSB.
HSSI Write Data CSR [31:16] Maximum TX frame size
HSSI Write Data CSR [15:0] Maximum RX frame size

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