Ethernet Subsystem Intel® FPGA IP User Guide: Early Access Customer Release

ID 773413
Date 4/14/2023

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Document Table of Contents

1.2. Getting Started

The Ethernet Subsystem Intel FPGA IP parameter editor allows you to quickly configure your custom IP variation.

Use the following steps to specify IP core options and parameters in the Intel® Quartus® Prime Pro Edition software version 23.1.

  1. In the IP Catalog, locate and select Ethernet => Ethernet Subsystem Intel FPGA IP (Early Access). The New IP Variation window appears.
  2. Specify a top-level name for your new custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.ip.
  3. Click OK. The parameter editor appears.
  4. Specify the parameters for your IP core variation. Refer to Parameter Editor Parameters, for information about specific IP core parameters.
  5. Optionally, to generate a simulation testbench or compilation and hardware design example, follow the instructions in Ethernet SS IP Example Design.
  6. Click Generate HDL. The Generation dialog box appears.
  7. Specify output file generation options, and then click Generate. The IP variation files generate according to your specifications.
  8. Click Close. The parameter editor adds the top-level.ip file to the current project automatically. If you are prompted to manually add the .ip file to the project, click Project > Add/Remove Files in Project to add the file.
  9. After generating and instantiating your IP variation, make appropriate pin assignments to connect ports and set any appropriate per-instance RTL parameters.