External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide

ID 772538
Date 10/02/2023

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Document Table of Contents

2. Intel Agilex® 7 M-Series FPGA EMIF IP – Introduction

Intel's fast, efficient, and low-latency external memory interface (EMIF) intellectual property (IP) cores interface with today's higher speed memory devices.

You can implement the EMIF IP core functions through the Intel® Quartus® Prime software.

The External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP (referred to hereafter as the Intel Agilex® 7 M-Series EMIF IP) provides the following components:

  • A physical layer interface (PHY) which builds the data path and manages timing transfers between the FPGA and the memory device.
  • A memory controller which implements all the memory commands and protocol-level requirements.

For information on the maximum speeds supported by the external memory interface IP, refer to the External Memory Interface Spec Estimator, available here: https://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/external-memory-interfaces-support/emif.html.