External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide

ID 772538
Date 10/02/2023

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11.6. Guidelines for Developing HDL for Traffic Generator

If you are not getting the expected response on the AXI bus when using your own traffic generator to test your EMIF IP on hardware, ensure that your traffic generator meets the following guidelines.
  1. The traffic generator issues transactions only after calibration has completed successfully. You can check the calibration status by using the AXI-Lite interface. In the EMIF example design, the cal_done_rst_n port on the ed_synth_axil_driver_0 corresponds to the calibration status. A value of cal_done_rst_n=1 indicates that the calibration has completed and passed.

    Your traffic generator can begin to issue AXI-compliant transactions only after cal_done_rst_n=1.

    Figure 77.  cal_done_rst_n in ed_synth_axil_driver_0
  2. Ensure that all the AXI ports on the EMIF IP are driven by registers. To prevent registers from being merged and synthesized away, add the don't merge and preserve attributes to the registers driving the AXI port in your HDL.
    Figure 78. Specifying dont_merge and preserve Attributes to all Registers Driving AXI Port