External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide

ID 772538
Date 10/02/2023

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7.3.5. RDIMM, UDIMM, and SODIMM Break-in Layout Guidelines

The following figures show recommended signal and ground cutout and via transition, and placement patterns for RDIMMs, UDIMMs, and SODIMMs.

Intel recommends placing the vias on the connector pad, or with a short trace connected to connector pad. The placement of transition vias is critical to avoid stubs during transition to connector pads. It is also recommended to void under connector pads to avoid large capacitance and reflection in this area, and to control the impedance at the DIMM pads.

Figure 39. Recommended Signal and Ground Cutouts
Figure 40.  Recommended Signal and Ground Via Transitions