External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide

ID 772538
Date 10/02/2023

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Document Table of Contents

4.1.10. s0_axi4lite_rst_n for EMIF

Axilite reset interface

Table 35.  Interface: s0_axi4lite_rst_nInterface type: reset
Port Name Direction Description
s0_axi4lite_rst_n input Axilite reset