External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide

ID 772538
Date 10/02/2023

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8.3.3. DDR Differential Signals Routing

DQS and CLK signals in the DDR interface are differential signals and must be routed on the PCB as differential signals unless there is a limitation for PCB routing, such as having a very small pitch at DRAM.

You should have a symmetrical fan-out routing at the FPGA pin field. Non-symmetrical routing for differential signals causes shifting on common-mode voltage and contributes to reduced timing margins at the receiver. The following figures show the recommended differential routing at the FPGA pin field for DQS/CLK signals.

Figure 58. Symmetrical Routing of Differential Signals (DQS/CLK) at FPGA Pin Field, with Length/Skew Matching Between P/N Lanes After FPGA Device Edge
Figure 59. Single-Ended Routing for Differential Signals (DQS/CLK) at DRAM Pin Field with Very Small Pitch and Skew Matching at Edge of DRAM Pin Field

Intel recommends implementing length and skew matching for differential signals immediately after the FPGA device to avoid additional shifting on differential signals common mode voltage.

In cases where very small DRAM device pitch limits the implementation of symmetrical routing at the DRAM pin field for differential signals, it is recommended to route the differential signals as single-ended signals within the DRAM pin field, ensuring to maintain the same impedance while changing from differential to single-ended configuration. Designers must also keep the same length of routing for each P and N single-ended lane within the DRAM pin field. The skew matching between P and N lanes must be applied before reaching the DRAM pin field.