External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide

ID 772538
Date 10/02/2023

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Document Table of Contents

8.3.7. LPDDR5 Simulation Strategy

The simulation strategy has two parts:

  • Data Signal signal integrity simulation with respect to their DQS on the worse signal integrity of a data group (considering the longest routing and maximum vertical crosstalk between signals).
  • CS/CTRL/CMD signal integrity simulation with respect to their CLK signals on the worst signal integrity of those signals (considering the longest routing and maximum vertical crosstalk between signals).

Intel recommends that the signal integrity engineer review the layout and pick the worst data group (select a victim and surrounded aggressors and DQS in the group) that has the worst signal integrity on the layout (that is, the worst cross talk coupling between deep vertical vias), long trace/PCB routing and maximum reflection on the routing path due to long via stubs if backdrilling is not applied.

Designers must perform signal integrity simulation of the board layout for the selected victim surrounded by aggressor signals.

The channel analysis must be performed in the time domain (using PRBS pattern for I/O signal generator) while the channel is built by using actual per-pin package model at both ends, PCB model in the format of scattering parameter along with I/O buffer model at both ends. I/O buffer IBIS model was used for DDR4 interface SI simulation; however, LPDDR5 requires an IBIS AMI buffer model (due to the equalizations/FFE/DFE at both TX and RX) at both ends to recover the data. Eye diagram is evaluated after the simulation to meet eye specification at both ends.

Note: Currently the FPGA LPDDR5 GPIO-B buffer IBIS AMI model is not available for designers to do the signal integrity simulation. Designers are advised to follow strictly the PCB routing design guideline in this document to meet maximum supported data rate per selected configuration.