External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide

ID 772538
Date 10/02/2023

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Document Table of Contents Example of a DDR5 layout on Intel FPGA Platform Board

The following figure shows the layout example of a DDR5 x32 plus 8x ECC (3x DRAM Dual-Die Memory Down).

This layout is designed on a thick PCB (120mil stackup) using micro vias and through vias with backdrill. The DDR5 Data signal routing is on upper layers to avoid vertical crosstalk and achieve high performance; the CS/CTRL signals can be routed on deeper layers.

Figure 50. DDR5 32bits+ 8x bits ECC (3 x DRAMs Dual Die) PCB routing on an Intel FPGA Platform Board with thick stackup