External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide

ID 772538
Date 10/02/2023

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7.3.8. DDR5 Simulation Strategy

The simulation strategy has two parts:

  • Data Signal signal integrity simulation with respect to their DQS on the worse signal integrity of a data group (considering the longest routing and maximum vertical crosstalk between signals).
  • CS/CTRL/CMD signal integrity simulation with respect to their CLK signals on the worst signal integrity of those signals (considering the longest routing and maximum vertical crosstalk between signals).

Intel recommends that a signal integrity engineer review the layout and pick the worst data group (select a victim and surrounded aggressors and DQS in the group) that has the worst signal integrity on the layout (that is, the worst cross talk coupling between deep vertical vias), long trace/PCB routing and maximum reflection on routing path due to long via stubs if backdrilling is not applied.

Designers must perform signal integrity simulation of the board layout for the selected victim surrounded by aggressor signals.

Ensure that the channel analysis is performed in the time domain (using PRBS pattern for I/O signal generator) while the channel is built, by using the actual per-pin package model at both ends, and PCB model in the format of scattering parameter along with I/O buffer model at both ends. DDR5 requires an IBIS AMI buffer model (due to equalizations/FFE/DFE at both TX and RX) at both ends to recover the data. Evaluate the eye diagram after the simulation to ensure that the design meets eye specification at both ends.

Note: Currently the FPGA DDR5 GPIO-B buffer IBIS AMI model is not available for designers to do the signal integrity simulation. Intel recommends that designers strictly follow the PCB routing design guidelines in this chapter, to achieve the maximum supported data rate for the selected configuration.