External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide

ID 772538
Date 10/02/2023

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Document Table of Contents Hard Memory Controller Features

Table 23.  Features of the Intel Agilex® 7 M-Series Hard Memory Controller
Feature Description
Memory standards support

Supports DDR4, DDR5, and LPDDR5 SDRAM.

Memory devices support Supports the following memory devices:
  • Discrete (DDR4, DDR5, LPDDR5)
  • UDIMM (DDR5)
  • RDIMM (DDR5)
Interface protocols support
  • Supports the AXI4 interface.
Configurable memory interface width
  • DDR4 supports DQ widths: 16, 32, 40
    • Discrete component : 16, 16+ECC, 24, 32, 32+ECC, 40
    • DIMM : 64, 64 + ECC, 72
  • DDR5 supports DQ widths: 16, 16+ECC (1ch/2ch), 32, 32+ECC (1ch/2ch)
  • LPDDR5 supports DQ widths: 16 (1ch/2ch), 32 (1ch)
Maximum rank support 2 ranks with single slot.
Burst length support
  • DDR4: BL8
  • DDR5: BL16
  • LPDDR5: BL16
Efficiency optimization features
  • Open-page policy—by default, opens page on every access. However, the controller intelligently closes a row based on incoming traffic, which improves the efficiency of the controller especially for random traffic.
  • Pre-emptive bank management—the controller issues bank management commands early, which ensures that the required row is open when the read or write occurs.
  • Data reordering—the controller reorders read/write commands.
  • Additive latency—the controller can issue a READ/WRITE command after the ACTIVATE command to the memory bank prior to tRCD, which increases the command efficiency.
Starvation counter Ensures all requests are served before a predefined time-out period, which ensures that low priority access are not left behind while reordering data for efficiency.
Bank interleaving Able to issue read or write commands continuously to "random" addresses. You must correctly cycle the bank addresses.
On-die termination In DDR4, the controller controls the on-die termination signal for the memory. This feature improves signal integrity and simplifies your board design.
Refresh features
  • User-controlled refresh timing—optionally, you can control when refreshes occur and this allows you to prevent important read or write operations from clashing with the refresh lock-out time.
  • Per-rank refresh—allows refresh for each individual rank.
  • Controller-controlled refresh.
Power saving features
  • Low power modes (power down and self-refresh)—optionally, you can request the controller to put the memory into one of the two low power states.
  • Automatic power down—puts the memory device in power down mode when the controller is idle. You can configure the idle waiting time.
  • Memory clock gating.
Memory features
  • Bank group support—supports different timing parameters for between bank groups.
  • Command/Address parity—command and address bus parity check.
User ZQ calibration Long or short ZQ calibration request for DDR4.