External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide

ID 772538
Date 10/02/2023

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8.1.2. Intel Agilex® 7 FPGA EMIF Calibration IP Parameter Descriptions

The following topics describe the parameters available on each tab of the IP parameter editor, which you can use to configure your IP. Each parameter with an adjacent checkbox can be auto-computed. The checkbox to the left of the parameter controls whether its value is auto-computed (true) or set manually (false). If there is no checkbox to the left of a parameter, then it must be set manually.
Table 147.  Group: High-Level Parameters
Display Name Description
Unique Instance ID for the Calibration IP

Instance ID

(Identifier: INSTANCE_ID)

Calibration IP is part of Bank Adjacent Pair

Calibration IP is part of Bank Adjacent Pair


Number of Peripheral IPs

Number of Peripheral IPs (EMIFs, PHYLites) to be calibrated


Number of Standalone I/O PLLs

Number of Standalone I/O PLLs to calibrate

(Identifier: NUM_CALBUS_PLLS)

AXI-L Subordinate Port Mode

AXI-L subordinate port can be disabled, or can be used in one of two modes: directly exported to fabric, or connect to the NoC (i.e. to a TNIU)

(Identifier: PORT_S_AXIL_MODE)