External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide

ID 772538
Date 10/02/2023

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Document Table of Contents LPDDR5 Discrete Component/Memory Down Topology (1 Rank or 2 Rank, up to 64 Bit Interface)

LPDDR5 memory down support is available in two configurations: single rank or dual rank, up to 64 bit interface.

There are four DRAM interface signal groupings: Data Group, Command-Address Group, Control Group, and Clock Group. The connection between the FPGA and DRAM uses point-to-point topology for Data, Command/Address, Control, and Clocks, as shown in the following figure.

Figure 61. Point-to-Point Connection for Data, CA, CTRL, and Clock Signals Topology for LPDDR5

The LPDDR5 interface does not support a traditional dual-directional data-strobe architecture. However, two single-directional data strobes such as Write Clock (WCK) for Write Operations and an optional Read Clock (RDQS) for Read Operations are supported.

The following two figures show the connection topology for DQ, WCK signal and CA, CLK, CTRL signals for LPDDR5.

Figure 62. WCK Signals Topology for LPDDR5 Memory Down, T-Line Connection, Depending on EMIF Topology

Figure 63. CS, CLK, CTRL Signals Topology for LPDDR5 Memory Down: Daisy or T-Line Connections, Depending on EMIF Topology