External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide

ID 772538
Date 10/02/2023

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7.3. DDR5 Board Design Guidelines

This section provides board layout design recommendations and guidelines for Intel Agilex® 7 M-Series FPGAs, with GPIO-B (input/output) silicon implementation to support DDR5.

This PCB layout guideline covers various supported DDR5 topologies along with maximum supported data rate that you can use for a successful PCB design.

A successful PCB design requires not only following the topology and routing guidelines here, but must also meet PDN design requirements.

For related information, refer also to the Intel Agilex® 7 F, I, and M-Series PDN design guidelines and the Intel Agilex® 7 high speed transceiver PCB design guidelines, available on the Intel website.