External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide

ID 772538
Date 10/02/2023

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8.3.1. PCB Stack-up and Design Considerations

The following figure shows an example of an 18-layer PCB stackup that has been used for LPDDR5 on an Intel platform board. You may use other stackups (thin such as PCIE board, or thick board), provided you follow the recommendations in these guidelines.

Figure 53. 18-Layer Thin Board Type-4 PCB with Micro Via, Stacked Via, Buried Via and Through Via

The following figure shows an example of a 22-layer thick PCB stackup, as used with some Intel platform boards and development kits.

Figure 54. 22-Layer Thick Type-4 Board Stack-up, High Performance with Micro Via and PTH, with and without Backdrill

A high-quality type-4 PCB uses not only plated-through-hole (PTH) vias to connect from the top to bottom layer, but also stacked vias, micro vias, and buried vias to connect between layers. For example, a full-height stacked via of an 18 layer PCB consists of a combination of dual-stacked micro vias and buried vias. The following figure shows a cross-sectional comparison of a PTH and stacked via.

Figure 55. Cross-sectional Comparison of Plated-Through Hole Via and Stacked Via

To support maximum data rate operation, LPDDR5 board design requires a high-quality PCB stackup using micro vias, buried vias, or stacked vias to reduce crosstalk for high performance. Reducing the length of signal via is essential to minimizing the crosstalk between signals.

A type-3 PCB with zero-built up layers and PTH vias which is used to implement a DDR4 design can also be used for LPDDR5 designs if backdrill is implemented to reach the maximum supported data rate.