External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide

ID 772538
Date 10/02/2023

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Document Table of Contents Example of an LPDDR5 Layout on an Intel® FPGA Platform Board

The following figures show the layout example of a single rank LPDDR5 x 32-bit device with a pitch size of 0.7×0.8mm on an Intel FPGA platform design.

This example has been designed on a thick PCB (120mil stackup) using micro vias and through vias with backdrill. The LPDDR5 signal routing is on upper layers to avoid vertical crosstalk on interface and achieve high performance.

Figure 72. Board Layout and Via Pattern for Single Rank LPDDR5 x32 device on an Intel FPGA Platform Design

In addition, the following figure shows a LPDDR5 64-bit device board routing sample with pitch dimension of 0.4×0.4mm. The microvia has been used for via transitions on this interface.

Figure 73. Board Via Pattern for LPDDR5 64-bit Device