F-Tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 1/24/2024
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4.4. Guidelines for F-Tile Reference and System PLL Clocks Intel® FPGA IP Usage

You must adhere to the following guidelines to correctly use the F-Tile Reference and System PLL Clocks Intel® FPGA IP:
  • The F-Tile Reference and System PLL Clocks Intel® FPGA IP must always connect to the F-Tile PMA/FEC Direct PHY Intel® FPGA IP or protocol IPs. You cannot compile or simulate the F-Tile Reference and System PLL Clocks Intel® FPGA IP as a standalone IP.
  • Once the reference clock for the system PLL is up; it must be stable; it must be present throughout the device operation and must not go down. If you are not able to adhere to this, you must reconfigure the device. After the temporary loss of the system PLL reference clock, you may observe that the first try of device reconfiguration fails. If that happens, you should try to reconfigure the device a second time.
  • You must connect the reference clock and system PLL output ports of F-Tile Reference and System PLL Clocks Intel® FPGA IP to input of F-Tile PMA/FEC Direct PHY Intel® FPGA IP as shown in Port Connection Guidelines between F-Tile Reference and System PLL Clocks Intel® FPGA IP and F-Tile PMA/FEC Direct PHY Intel® FPGA IP or protocol IPs.
  • You must ensure the reference clock and system PLL frequencies specified in F-Tile Reference and System PLL Clocks Intel® FPGA IP match reference clock and system PLL frequencies specified in F-Tile PMA/FEC Direct PHY Intel® FPGA IP or protocol IPs. Any mismatch in frequency results in Intel® Quartus® Prime Pro Edition software Support-Logic Generation failure.
  • You must enable at least one system PLL per F-tile because this is a requirement for F-tile configuration to pass successfully. Enabling at least one system PLL is required even when the data path is using PMA clocking mode. If your design has one system PLL enabled to be used for system PLL clocking, you do not need a separate system PLL for F-tile configuration. When you use the system PLL only for F-tile configuration (that is, when all lanes use the PMA clocking mode) the following guidelines apply:
    • You must enable System PLL #0. If you enable System PLL #1 or System PLL #2, the Intel® Quartus® Prime Pro Edition software Support-Logic Generation step fails.
    • The system PLL output must be unconnected. This is the only exception where you can leave the system PLL output unconnected. In all other scenarios you must always connect the system PLL output to F-Tile PMA/FEC Direct PHY Intel® FPGA IP or protocol IPs.
    • If you are not using the FGT PMA, the reference clock to system PLL connection is not necessary (that is, you do not need to connect the reference clock); however, if you connect a reference clock, the configuration completes faster.
    • If you are using the FGT PMA, the reference clock to system PLL connection is necessary (that is, you must connect the reference clock).
  • When you instantiate multiple interfaces or protocol-based IP cores within a single F-tile, you must use only one instance of the F-Tile Reference and System PLL Clocks Intel® FPGA IP to configure the following:
    • All reference clocks for the FGT PMA (up to 10) and the FHT PMA (up to 2) that are required to implement those multiple interfaces within a single F-tile.
    • All FHT common PLLs (up to 2) that are required to implement those multiple interfaces within a single F-tile.
    • All system PLLs (up to 3) that are required to implement those multiple interfaces within a single F-tile.
    • All reference clocks for system PLLs (up to 8, shared with the FGT PMA) that are required to implement those multiple interfaces within a single F-tile.
When you design multiple interfaces or protocols based IP cores within a single F-tile, you can only use three system PLLs. For example, you can use one system PLL for PCIe and two for Ethernet and other protocols. However, there are other use cases where you can use all three for various interfaces within the Ethernet and PMA direct digital blocks. As there are only three system PLLs, multiple interfaces or protocol based IP cores with different line rates may have to share a system PLL. While sharing a system PLL, the interface with the highest line rate determines the system PLL frequency, and the interfaces with the lower line rates must be overclocked.
All reference clock, system PLL and common PLL selection in the IP parameter editor are logical. The .qsf assignments map these logical selection to physical resources.
  • Although system PLL reference clock source lists ten reference clocks (reference clock #0 to #9), only eight physical reference clocks can clock the system PLL. For example, you could select reference clock #10 as the system PLL reference clock source, but this must be physically mapped to FGT/System PLL reference clock location 0 to 7 by specifying the .qsf assignments.
  • When you enable the FGT CDR Output (RX recovered clock output), you must physically map the corresponding FGT PMA to FGT Quad 2 or 3, and you must physically map the FGT CDR Output (RX recovered clock output) to the FGT reference clock location 8 or 9 (configured as output).
  • The total number of FGT/system PLL reference clocks and FGT CDR clock out that are enabled must not exceed 10.