Visible to Intel only — GUID: ixt1660929740390
Ixiasoft
Visible to Intel only — GUID: ixt1660929740390
Ixiasoft
3.5.2.1. TX Parallel Data Mapping Information for SATA Protocol Mode for Different Configurations
- PMA electrical idle feature
- Squelch detect feature
- Signal detect feature
The final support for these features is planned in a future version of the Intel® Quartus® Prime Pro Edition software.
When SATA is selected for one PMA lane, the tx_parallel_data bus width is reduced from an 80-bit interface to a 76-bit interface. The formula outlined in Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath to calculate the total tx_parallel_data bus is valid except the interface bus width is now reduced to 76-bit from 80-bit. The upper 4 bits are configured to fgt_tx_pma_elecidle bus signal. There is no change to the rx_parallel_data bus width.
Total tx_parallel_data Bit Width Equation for SATA:
tx_parallel_data[(76*N)-1:0]
fgt_tx_pma_elecidle [(4*N)-1:0]
Where:
- N = Number of PMA lanes value from 1 to 16.
Refer to Variables Defining Bits for the Interfacing Ports in Port and Signal Reference for full variable definitions.
Example 1: Total tx_parallel_data Bit Width with 1 SATA Link (N=1) and 32-bit PMA Width
tx_parallel_data [(76*1)-1:0] = tx_parallel_data [75:0], fgt_tx_pma_elecidle [3:0]
Example 2: Total tx_parallel_data Bit Width with 2 SATA Links (N=2) and 32-bit PMA Width
tx_parallel_data [(76*2)-1:0] = tx_parallel_data [151:0], fgt_tx_pma_elecidle [7:0]
PMA Configuration | Bits | TX Parallel Data | RX Parallel Data |
---|---|---|---|
FGT PMA Width = 8, 10, 16, 20, 32 Single Width SATA (One PMA Lane [N=1] with PMA Width ≤ 32) |
75 | Write Enable for TX Core FIFO in Elastic Mode | No change, refer to TX and RX Parallel Data Mapping Information (PMA Lanes, N = 1) with the same PMA configuration. |
35 | TX PMA Interface Data Valid | ||
[D-1]:0 | TX Data | ||
FGT PMA Width = 8, 10, 16, 20, 32 Double Width SATA (One PMA Lane [N=1] with PMA Width ≤ 32) |
75 | Write Enable for TX Core FIFO in Elastic Mode | No change, refer to TX and RX Parallel Data Mapping Information (PMA Lanes, N = 1) with the same PMA configuration. |
[D -1 + 36]:36 | TX Data (Upper Data Bits) | ||
35 | TX PMA Interface Data Valid | ||
[D -1]:0 | TX Data (Lower Data Bits) | ||
RS-FEC Enabled, N = number of FEC lanes, X = fec stream index = (0:N-1) | |||
FGT PMA Width = 32 Double Width SATA (One PMA Lane [N=1] with PMA width = 32) |
74 | TX Deskew Bit | No change, refer to TX and RX Parallel Data Mapping Information (Number of PMA Lanes (N) = 1) with the same PMA configuration. |
73 | TX Alignment Marker | ||
68:36 | TX Data (Upper 33 Bits) | ||
35 | TX PMA Interface Data Valid Bit | ||
32:2 | TX Data (Lower 31 Bits) | ||
1:0 | Sync head |