F-Tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 1/24/2024
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3.6.5. FGT RX CDR Clock Output

You can enable the rx_cdr_divclk_link0 port to output the FGT RX CDR clock from the RX PMA to the reference clock pin. You can enable two FGT RX CDR clock outputs for each F-Tile.
  • One output port can connect to reference clock 8. You must place the source in quad 2. You can enable or disable this port and change its source through the RX CDR clock register of any quad 2 PMA lane.
  • The other output port can connect to reference clock 9. You must place the source in quad 3. You can enable or disable this port and change its source through RX CDR clock register of any quad 3 PMA lane.
The output frequency of rx_cdr_divclk_link0 = cdr_f_ref_hz / cdr_n_counter, where:
  • cdr_f_ref_hz is the RX CDR reference clock frequency, which is the FGT reference clock frequency.
  • cdr_n_counter is the pre-divider on the RX path.
To get the cdr_n_counter value, follow the steps below:
  1. Run Support-Logic Generation in the Intel® Quartus® Prime Pro Edition software.
  2. Open the Compilation Report, and go to Logic Generation ToolIP Parameter Settings Report.
  3. Search for cdr_n_counter in the report.
  4. You can also search for cdr_f_ref_hz to confirm the FGT reference clock frequency.
Figure 83. Compilation Report to Obtain the cdr_n_counter Value